【论文】SYSTEM AND CIRCUIT DESIGN TECHNIQUES

iaman

3. GSM/WCDMA/WiFi TRIPLE-STANDARD TRANSCEIVER ARCHI-
TECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 WLAN Transceiver Architecture . . . . . . . . . . . . . . . . . . . 31
3.1.1 Modulation Schemes in WiFi . . . . . . . . . . . . . . . . . 32
3.1.2 WiFi Transmitter Architecture . . . . . . . . . . . . . . . . 34
3.1.3 WiFi Receiver Architecture . . . . . . . . . . . . . . . . . . 35
3.2 WCDMA Transceiver Architecture . . . . . . . . . . . . . . . . . . 36
3.2.1 Modulation and Multiple Access Schemes in WCDMA . . . 36
3.2.2 WCDMA Transmitter Architecture . . . . . . . . . . . . . . 38
3.2.3 WCDMA Receiver Architecture . . . . . . . . . . . . . . . . 39
3.3 GSM Transceiver Architecture . . . . . . . . . . . . . . . . . . . . 40
3.3.1 Modulation Scheme in GSM . . . . . . . . . . . . . . . . . . 40
3.3.2 GSM Transmitter Architecture . . . . . . . . . . . . . . . . 41
3.3.3 GSM Receiver Architecture . . . . . . . . . . . . . . . . . . 41
3.4 Triple-Standard Frequency Synthesizer Architecture . . . . . . . . . 42
3.5 GSM/WCDMA/WiFi Transceiver Architecture . . . . . . . . . . . 45
4. GSM/WCDMA/WiFi TRIPLE-STANDARD RECEIVER SPECIFICA-
TIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1.1 Noise Figure and Noise Floor . . . . . . . . . . . . . . . . . 48
4.1.2 IIP3 and IIP2 . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1.3 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2 System Level Speci¯cation . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.1 Sensitivity Test . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.2 Intermodulation Test . . . . . . . . . . . . . . . . . . . . . . 55
4.2.3 Spurious Response Test . . . . . . . . . . . . . . . . . . . . 58
4.2.4 Adjacent Channel Selectivity Test (ACS Test) . . . . . . . . 60
4.2.5 In-band and Out-of-band Blocker Test . . . . . . . . . . . . 65
4.2.6 Summary of System Speci¯cation . . . . . . . . . . . . . . . 66
4.3 Block Level Speci¯cation . . . . . . . . . . . . . . . . . . . . . . . . 66
5. GSM/WCDMA/WiFi TRIPLE-STANDARD §¢ ADC DESIGN AND
SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.1 Introduction to §¢ ADCs . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.1 Nyquist-Rate A/D Converter . . . . . . . . . . . . . . . . . 74
5.1.2 Over-Sampling A/D Converter . . . . . . . . . . . . . . . . 75
5.1.3 §¢ A/D Converter . . . . . . . . . . . . . . . . . . . . . . . 77
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5.1.4 Performance Metrics of §¢ A/D Converter . . . . . . . . . 80
5.2 Overview of High Speed, Multi-Standard §¢ ADCs . . . . . . . . . 81
5.2.1 Architectures of §¢ ADCs . . . . . . . . . . . . . . . . . . 81
5.2.2 State-of-the-art for §¢ ADCs in Wireless Receivers . . . . . 99
5.3 The Proposed High-Speed Multi-Standard §¢ ADC . . . . . . . . 102
5.3.1 Architecture Selection . . . . . . . . . . . . . . . . . . . . . 103
5.3.2 System Level Design . . . . . . . . . . . . . . . . . . . . . . 106
5.4 §¢ Modulator Modeling and Analysis . . . . . . . . . . . . . . . . 112
5.4.1 Modeling of Non-ideal OTA . . . . . . . . . . . . . . . . . . 113
5.4.2 Capacitor Mismatch Analysis . . . . . . . . . . . . . . . . . 120
5.4.3 Multi-bits Quantizer Nonlinearity Analysis . . . . . . . . . . 123
5.4.4 Comparator o®set and Hysteresis analysis . . . . . . . . . . 125
5.5 Simulation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6. GSM/WCDMA/WiFi Tri-Standard SC §¢ ADC Implementation . . . . 129
6.1 Switch Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.1.1 Delayed and Non-Delayed Integrators . . . . . . . . . . . . 130
6.1.2 Timing Issue in Non-delayed Integrator and the Feedback `a' 136
6.2 Capacitor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3 Design of Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.1 Design of OTA . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.2 Design of Switch . . . . . . . . . . . . . . . . . . . . . . . . 149
6.4 Implementation of Comparators . . . . . . . . . . . . . . . . . . . . 156
6.5 Implementation of Multibit Quantizer . . . . . . . . . . . . . . . . 161
6.6 Implementation of Multi-Phase Clock Driver . . . . . . . . . . . . . 162
6.7 Prototype and Simulation Results . . . . . . . . . . . . . . . . . . . 164
6.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

iaman

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denap

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denap

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denap

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zying

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