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发表于 2008-4-17 22:40:51
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显示全部楼层
module mux(oe,dacs,clk,dadb);
output oe,dacs;
output[7:0] dadb;
input clk;
reg[7:0] dadb;
reg[2:0] en;
always @(posedge clk)
begin
if(en==0) dadb=8'b11111111;
else dadb=8'b00000000;
end
always @(posedge clk)
begin
en=en+1;
end
en需要有一个reset值吧,不然simulaiton都不行 |
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