PLL博士论文_全集成频率综合器_作者为Allen, Phillip E.的学生Zhang, Benyong

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A 2.4 GHz, low power, fully-integrated CMOS frequency synthesizer for wireless communications.  
作者             Zhang, Benyong.;  
学校            Georgia Institute of Technology.  
指导老师     Allen, Phillip E.   
摘要　
A low phase noise/spur, high switching speed frequency synthesizer, which features a low power consumption, a high level of integration, and a low cost is highly desirable for wireless communications. A conventional type-II charge pump PLL frequency synthesizer typically has a relatively slow switching speed. The continuous time RC loop filter is sensitive to process and temperature variations.;A type-I charge pump PLL frequency synthesizer is proposed in this work. The stabilization of the closed loop system is achieved by using a discrete-time loop filter. The type-I system architecture leads to fast switching speed. The discrete time loop filter provides isolation between the phase/frequency detector and the VCO tuning node. Hence a good spur performance can be achieved. The proposed PLL frequency synthesizer is more suitable for integration.;To demonstrate the performance of the proposed type-I charge pump PLL frequency synthesizer architecture, a prototype 2.4GHz frequency synthesizer for the Bluetooth standard was developed. Design, analysis and extensive simulations were carried out at both system level and circuit level. The test chip was fabricated in a 0.25um CMOS process. The measurement results of the prototype PLL frequency synthesizer verified the principle of the proposed architecture. A switching time of 30us and a reference spur of ?62dBc were achieved.;Compared with the state-of-the-art CMOS frequency synthesizer based on conventional type-II charge pump PLL frequency synthesizer architecture for the same Bluetooth application reported in [3], the switching speed of the prototype type-I charge pump PLL frequency synthesizer is about five times faster than that of the conventional frequency synthesizer. The reference spur performance of the prototype is 9dB better than that of conventional frequency synthesizer. The phase noise of the prototype at 550kHz offset and 2MHz offset are 1dB better and 10 dB better than that of the conventional frequency synthesizer, respectively. A typical conventional frequency synthesizer [3] has an off-chip continuous time loop filter. The prototype features a discrete time on-chip loop filter except one off-chip capacitor for testing purpose, which could be integrated. In conclusion, the prototype type-I charge pump frequency synthesizer achieves a much better overall performance than the conventional CMOS type-II charge pump PLL frequency synthesizer.

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