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发表于 2008-4-22 09:14:20
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This thesis reviews the problems of ESD in the IC industry and the standard models used
to characterize ESD protection-circuit performance. Previous approaches to ESD circuit
design are discussed, including design theory and specific design examples. Transmissionline
pulsing (TLP), a relatively new ESD characterization and analysis test method, is
presented. This test method offers many advantages over standard characterization
techniques, including the ability to extract critical parameters of an ESD protection circuit
and to determine the failure level of a circuit over a wide range of ESD stress durations.
Dependencies of ESD circuit performance on critical process parameters of a CMOS
technology are discussed. Two-dimensional numerical device simulation techniques are
presented for modeling ESD in circuits, including electrothermal simulation and a curvetracing
algorithm, detailed in an appendix, used to guide simulations through complex
current-voltage (I-V) curves. Results are given for TLP experiments run on parametric
ESD structures created in a 0.5μm CMOS technology, including MOSFET snapback I-V
characteristics and failure thresholds. Results of calibrated simulations are also presented
and compared to experiments. Details of the simulation calibration procedure are
provided. |
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