Low Power FIR Filter的code.

lxandlj

简介:
This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD's Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system.

The power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design.

The design was produced at the gate level, enabling low-power architecture to be implemented using the extracted VHDL netlists. Each part of the design is explained within the design report (FIRLowPowerFinalReport.doc), along with the techniques for the operation of the system.

luansh0310

XIEXIE