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Due to its potential to greatly accelerate a wide variety of applications, reconfigurable
computing has become a subject of a great deal of research. Its key feature is the ability
to perform computations in hardware to increase performance, while retaining much of
the flexibility of a software solution. In this survey, we explore the hardware aspects of
reconfigurable computing machines, from single chip architectures to multi-chip
systems, including internal structures and external coupling. We also focus on the
software that targets these machines, such as compilation tools that map high-level
algorithms directly to the reconfigurable substrate. Finally, we consider the issues
involved in run-time reconfigurable systems, which reuse the configurable hardware
during program execution.
Categories and Subject Descriptors: A.1 [Introductory and Survey]; B.6.1 [Logic
Design]: Design Style—logic arrays; B.6.3 [Logic Design]: Design Aids; B.7.1
[Integrated Circuits]: Types and Design Styles—gate arrays
General Terms: Design, Performance
Additional Key Words and Phrases: Automatic design, field-programmable, FPGA,
manual design, reconfigurable architectures, reconfigurable computing, reconfigurable
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