STA--set timing_remove_clock_reconvergence_pessimism

HLDDTOP

DESCRIPTION
       When this variable is true (the default), the tool removes clock recon-
       vergence pessimism from  slack  calculation  and  minimum  pulse  width
       checks.

       Clock  reconvergence pessimism (CRP) is a difference in delay along the
       common part of the launching and capturing clock paths.  The most  com-
       mon causes of CRP are reconvergent paths in the clock network, and dif-
       ferent min and max delay of cells in the clock network.

       CRP is independently calculated for rise and fall clock paths.  You can
       use  the  timing_clock_reconvergence_pessimism  variable to control CRP
       calculation with respect to transition sense.  In the case of the  cap-
       turing  device  being a level-sensitive latch two CRP values are calcu-
       lated:
       o crp_open, which is the CRP corresponding to the opening edge  of  the
         latch
       o  crp_close, which is the CRP corresponding to the closing edge of the
         latch

       The required time at the latch is increased by the  value  of  crp_open
       and  therefore  reduce  the  amount of borrowing (if any) at the latch.
       Meanwhile, the maximum time borrow allowed at the latch is affected  by
       shifting the closing edge by crp_close.

       CRP  is  calculated  differently for minimum pulse-width checks.  It is
       given as the minimum of (maximum  rise  arrival  time  -  minimum  rise
       arrival  time)  and  (maximum  fall arrival time - minimum fall arrival
       time) at the pin where the check is being made.

       If the si_enable analysis variable is set to true, delays in the  clock
       network could also include delta delays resulting from crosstalk inter-
       action. Such delays are dynamic in nature, that is, they can vary  from
       one clock cycle to the next, causing different delay variations (either
       speed-up or slow-down) on the same network, but during different  clock
       cycles.

       PrimeTime SI considers delta delays as part of the CRP calculation only
       if the type of timing check deployed derives its  data  from  the  same
       clock cycle.

       Similarly,  if  dynamic  annotations  have  been set on the design, the
       clock delays computed using these annotations are only used  to  calcu-
       late  CRP  if  type  of timing check deployed derives its data from the
       same clock cycle.   Such  dynamic  annotations  include  dynamic  clock
       latency,  which can be specified with the set_clock_latency command, or
       dynamic rail voltage, which can be specified with the  set_rail_voltage
       command.

       In   transparent-latch   based   designs,   you  should  set  the  tim-
       ing_early_launch_at_borrowing_latches  variable  to  false  when  clock
       reconvergence  pessimism  removal (CRPR) is enabled. In this case, CRPR
       applies even to paths whose startpoints are borrowing, leading to  bet-
       ter pessimism reduction overall.

       Any  effective  change in the setting of the timing_remove_clock_recon-
       vergence_pessimism variable causes full update_timing.  You cannot per-
       form  one  report_timing operation that considers CRP and one that does
       not without full update_timing in between.

       Limitations: CRPR does not support paths that  fan  out  directly  from
       clock  source  pins  to  the data pins of sequential devices. To enable
       support for such paths,  set  the  timing_crpr_remove_clock_to_data_crp
       variable to true.