猎头职位】ASIC Verification Engineer/ASIC DFT VERIFICATION

bestgrace

1. ASIC Verification Engineer



RESPONSIBILITIES:

- Develop and maintain verification environment at both full chip & unit level

- Develop and execute verification plan

- Develop BFM

- Code/functional coverage analysis

- Responsible for running both RTL & gate level simulation



MINIMUM REQUIREMENTS:

- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC verification

- Possess knowledge in at least one of the below areas

o HDCP/TMDS/LVDS/DisplayPort

o Blending, color space conversion

o Image up and down sampling

- Strong problem solving and analytical skills

- Must be proficient in Verilog HDL

- Must be strong in Perl programming, or strong in Python/Ruby programming

- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)

- Working knowledge in C/C++, Makefile

- Verilog PLI experience is a plus



2. ASIC DFT VERIFICATION Engineer



Responsibilities:

- Develop and maintain DFT verification environment at full chip  
- Develop test DFT cases and procedure

- Responsible for running both RTL & gate level simulation

-Generate test vectors and post silicon validation



Requirements:

- BSEE required, MSEE preferred.

- 2+ years of experience in DFT/design field

-Strong logic Design and verification back ground

- Possess strong Knowledge of DFT (scan insertion, MBIST, JTAG and etc.)

- Proficient in logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)

- Proficient in Verilog HDL

- Strong in Perl/tcl, programming

- Working knowledge in C/C++, Makefile

- Verilog PLI experience is a plus

- Strong problem solving and analytical skills





Grace Li

Principal Consultant & General Manager @ Hi-Talent Consulting Co. , Ltd.

上海芯相会企业管理咨询有限公司

E-Mail: bestgrace@qq.com

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