XILINX时钟错误，求助

shiyinjita

请问大家遇到过 下面的时钟问题没有？



Place:1138 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
   design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be
   placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that
   only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further
   information see the "Quadrant Clock Routing" section in the Spartan3a Family Datasheet.
   The competing Global / Side clock buffers for this device are as follows:
   BUFGMUX_X2Y1 :    BUFGMUX_X0Y2
   BUFGMUX_X2Y0 :    BUFGMUX_X0Y3
   BUFGMUX_X1Y1 :    BUFGMUX_X0Y4
   BUFGMUX_X1Y0 :    BUFGMUX_X0Y5
  BUFGMUX_X2Y11 :    BUFGMUX_X0Y6
  BUFGMUX_X2Y10 :    BUFGMUX_X0Y7
  BUFGMUX_X1Y11 :    BUFGMUX_X0Y8
  BUFGMUX_X1Y10 :    BUFGMUX_X0Y9
   BUFGMUX_X2Y1 :    BUFGMUX_X3Y2
   BUFGMUX_X2Y0 :    BUFGMUX_X3Y3
   BUFGMUX_X1Y1 :    BUFGMUX_X3Y4
   BUFGMUX_X1Y0 :    BUFGMUX_X3Y5
  BUFGMUX_X2Y11 :    BUFGMUX_X3Y6
  BUFGMUX_X2Y10 :    BUFGMUX_X3Y7
  BUFGMUX_X1Y11 :    BUFGMUX_X3Y8
  BUFGMUX_X1Y10 :    BUFGMUX_X3Y9
Phase 5.30  Global Clock Region Assignment (Checksum:6a77b3ee) REAL time: 25 secs
Total REAL time to Placer completion: 25 secs
Total CPU  time to Placer completion: 25 secs

Partition Implementation Status
-------------------------------
  No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       Clk100MOut10* |  BUFGMUX_X2Y0| No   |  394 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|        CLKOUT_IBUF* |  BUFGMUX_X0Y2| No   |  679 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|        ADCLK1_OBUF* |  BUFGMUX_X2Y1| No   |  300 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|              CLK4X* | BUFGMUX_X2Y11| No   |  120 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|         CLKLow_OUT* |  BUFGMUX_X1Y0| No   |   86 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|DivClkVhdl_u1/Cal_1K |              |      |      |            |             |
|                hz0* |  BUFGMUX_X3Y4| No   |   17 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|    usb_mcu_f0_IBUF* |  BUFGMUX_X0Y9| No   |   16 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|DivClkVhdl_u1/clk200 |              |      |      |            |             |
|                   * |  BUFGMUX_X1Y1| No   |    6 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|         sample_clk* |  BUFGMUX_X3Y2| No   |   11 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|serial_eeprom/clkdv_ |              |      |      |            |             |
|             out_ff* |  BUFGMUX_X3Y5| No   |   32 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|             Clk20M* | BUFGMUX_X1Y10| No   |   19 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|usbport/Capture_Star |              |      |      |            |             |
|                  t* |         Local|      |  215 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|     pwm_u/COUNT<2>* |         Local|      |    7 |  0.494     |             |
+---------------------+--------------+------+------+------------+-------------+
|trig_in_u1/trig_whol |              |      |      |            |             |
|                  e* |         Local|      |    2 |  2.094     |             |
+---------------------+--------------+------+------+------------+-------------+
|la_u/s16to1_inst/dat |              |      |      |            |             |
|              aout3* |         Local|      |    3 |  0.320     |             |
+---------------------+--------------+------+------+------------+-------------+
* Some of the Clock networks are NOT completely routed
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 234895 (Setup: 234843, Hold: 52, Component Switching Limit: 0)

我加了bufg后，逻辑跑起来就不太对了，请问大家有好的方法吗？

niulinux

only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further

好好检查一下你的时钟树结构和芯片的Datasheet，有可能发现问题。

timyang8292

Bufg资源应该是够的，查看一下是不是做了不合理的Area约束，或者Bufg的位置约束。
另外，bufg的链接使用是否正确，比如联级之类的。

Lawee

BUFG 例化在RTL中了没有？

shiyinjita

回复 3# timyang8292


    从什么地方看出bufg够用呢？》 我一直不会看这个，可以将一下吗？ 我只知道8个全局时钟，16个局部时钟。

shiyinjita

回复 4# Lawee


    恩，看了，RTL级别中有的，但是我没有固定，

shiyinjita

回复 2# niulinux


    恩，好的

2002cpp32

看来楼主的问题应该得到解决了。

shiyinjita

恩，呵呵，固定到全局时钟上，就好了

yanfabao

学习一下