xilinx 两个DCM 使用的问题，求解

jsjdezqh

可以考虑用第一个DCM的输出到第二个DCM的输入~~~

dlb05061131

回复 11# jsjdezqh


    我之前是这么干的，不过我好想看过XILINX的一个文档介绍，不建议这么干。因为第一个DCM的相位噪声会引入到第二个DCM。

billzhou06

你们好，我按照版主的设置之后，综合，翻译，映射通过了，但是布局布线报错啦，现象如下，本人新手，多多指教哈，谢谢
Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair.  The clock component <FPGA/DCM100/DCM_SP_INST> is placed at site <DCM_X2Y0>.  The clock IO/DCM site can be paired if they are placed/locked in the same quadrant.  The IO component <clk> is placed at site <PAD54>.  This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "FPGA/DCM100/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

tx00044011

好像是要用的PLL的。

tx00044011

回复 13# billzhou06


  我和你的情况一样，把最后两行粘到UCF中布局布线就通过了。记得去掉“<>”符合。

billzhou06

在UCF里加入上面两句的话，担心clk和clkin走的不是全局时钟线，会影响性能的吧