一级D触发器实现跨时钟域同步

tanjunjiang

最近在看一个i3c ip的代码，发现从机中做跨时钟域同步设计都使用的是1级DFF做同步，比如异步FIFO格雷码同步等，在代码的文件头中有如下描述：

for most modern process, the single flop model is fine, although the flop type may need to be changed by constraint for older process (e.g. a sync flop, which has a "gravity" to settle faster).
1 flop is fine in normal cases because the Q out metastable noise will be short enough in time for the paths used at the lower speed. that is ,there is ~40ns minimum to both settle and arrive settled at the other end.


请问有大佬有过类似的设计吗，所使用的工艺是什么？

tanjunjiang

   

janlesion 发表于 2022-5-24 09:31
个人认为，这与工艺应该没太大关系，主要是时钟频率相关，时钟周期远大于亚稳态的稳定时间，而且应该是特定 ...

感谢你的回复，根据你的观点我再去看看设计