formality 求助

shuke

可能是代码有问题。
从formality的文档里抄出来的：

FM-089 (error) RTL interpretation messages were produced during %s. Verification results may disagree with a logic simulator.          
DESCRIPTION          
Your simulation and verification results differ. These differences occur when a logic simulator and Formality do not interpret your HDL source code in exactly the same way.          
WHAT NEXT          
Modify your HDL source code according to the Synopsys HDL source development standards or use the "hdlin_warn_on_mismatch_message" variable to treat the message as a warning instead of an error.          

应该可以用>man FM-089看到的。
家里没有软件，没试。