formality 求助

jenny_guo

我在进行综合后RTL与网表形式验证，当读入了RTL代码和db后，set top竟然出错（网表还没读入呢）
Error: RTL interpretation messages were produced during link.
        Verification results may disagree with a logic simulator. (FM-089)
Error: Failed to set top design to 'r:/WORK/can_top' (FM-156)
0
这是怎么回事呢，请高手指教一下，不甚感激！

shuke

可能是代码有问题。
从formality的文档里抄出来的：

FM-089 (error) RTL interpretation messages were produced during %s. Verification results may disagree with a logic simulator.          
DESCRIPTION          
Your simulation and verification results differ. These differences occur when a logic simulator and Formality do not interpret your HDL source code in exactly the same way.          
WHAT NEXT          
Modify your HDL source code according to the Synopsys HDL source development standards or use the "hdlin_warn_on_mismatch_message" variable to treat the message as a warning instead of an error.          

应该可以用>man FM-089看到的。
家里没有软件，没试。

jenny_guo

谢谢，

nigolaskaiqe

Verification results may disagree with a logic simulator. (FM

bajie2918057

虚心学习

ICSEA88

学习了

icsystem

看是不是库没有读对

icsystem

永远都学习不完，这个东东

ck040521

那确实是 啊

chlor

把错误代码(FM-089)设为warning级别的，再试试！