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[资料] IC Compiler 1 Student & Lab Guide 2010.12(可搜寻 PDF)

[资料] IC Compiler 1 Student & Lab Guide 2010.12(可搜寻 PDF)

本帖最后由 ALUOp 于 2012-11-15 15:34 编辑

IC Compiler 1 Student & Lab Guide 2010.12(可搜寻 PDF)

At the end of this workshop you should be able to use IC Compiler to:
  • Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
  • Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
  • Perform placement and related optimizations to minimize timing violations, congestion, and power
  • Analyze congestion maps and timing reports
  • Perform pre-CTS power optimization
  • Perform clock tree synthesis
  • Analyze clock and timing results post-CTS
  • Route the clock nets
  • Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
  • Analyze and fix physical DRC and LVS violations
  • Perform functional ECOs
  • Perform chip finishing steps
  • Generate output files required for final validation/verification




另外还有:
SystemVerilog Verification UVM 1.1 Student & Lab Guide 2011.12(可搜寻 PDF)
SystemVerilog Testbench Student & Lab Guide 2011.12(可搜寻 PDF)
Design Compiler 1 Student & Lab Guide 2012.06 (可搜寻 PDF)
IC Compiler 1 Student & Lab Guide 2010.12 (可搜寻 PDF)
IC Compiler 2 CTS Student & Lab Guide 2010.03 (可搜寻 PDF)

IC Compiler 1.part1.rar (15 MB)

IC Compiler 1.part2.rar (15 MB)

IC Compiler 1.part3.rar (15 MB)

IC Compiler 1.part4.rar (15 MB)

IC Compiler 1.part5.rar (15 MB)

IC Compiler 1.part6.rar (15 MB)

IC Compiler 1.part7.rar (15 MB)

IC Compiler 1.part8.rar (2.61 MB)

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Thanks a lot

TOP

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