IC Compiler 1 Student & Lab Guide 2010.12（可搜寻 PDF）

ALUOp · 发表于 2012-11-15 15:04:33

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本帖最后由 ALUOp 于 2012-11-15 15:34 编辑

IC Compiler 1 Student & Lab Guide 2010.12（可搜寻 PDF）

At the end of this workshop you should be able to use IC Compiler to:

Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
Perform placement and related optimizations to minimize timing violations, congestion, and power
Analyze congestion maps and timing reports
Perform pre-CTS power optimization
Perform clock tree synthesis
Analyze clock and timing results post-CTS
Route the clock nets
Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
Analyze and fix physical DRC and LVS violations
Perform functional ECOs
Perform chip finishing steps
Generate output files required for final validation/verification

另外还有：
SystemVerilog Verification UVM 1.1 Student & Lab Guide 2011.12（可搜寻 PDF）
SystemVerilog Testbench Student & Lab Guide 2011.12（可搜寻 PDF）
Design Compiler 1 Student & Lab Guide 2012.06 （可搜寻 PDF）
IC Compiler 1 Student & Lab Guide 2010.12 （可搜寻 PDF）
IC Compiler 2 CTS Student & Lab Guide 2010.03 （可搜寻 PDF）

risccpu · 发表于 2012-11-16 11:15:30

very good, thanks!

pupukid · 发表于 2012-11-17 03:10:33

new ?

pupukid · 发表于 2012-11-17 07:02:18

IT's new

jhzhang · 发表于 2012-11-19 17:28:06

Thank you for share

yuanpin318 · 发表于 2012-11-22 08:37:53

谢谢你的分享

cmosa · 发表于 2012-11-22 09:46:29

感谢分享，非常好的资料

lodestar6666 · 发表于 2012-11-24 11:04:23

3xxxxxxxxx

snazzy · 发表于 2013-1-6 05:29:39

Dude
Thanks for sharing the wonderful docs on IC Compiler lab guide

Thanks a lot

snazzy · 发表于 2013-1-6 05:31:56

Thanks for sharing the docs
Thanks a lot

[资料] IC Compiler 1 Student & Lab Guide 2010.12（可搜寻 PDF）

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