PAL制式显示FPGA实现问题

logilas · 发表于 2010-3-30 00:41:09

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本帖最后由 logilas 于 2010-3-30 00:42 编辑

小弟用FPGA写了个PAL制式隔行扫描的显示模块，使用的是50HZ的帧频，产生奇偶场的复合消隐和复合同步控制信号，并送给DAV7123显示，但是在监视器上发现显示图像在上下抖动，但是接到LCD显示器上却只看到图像在左右晃动（图像数据本身无问题），不知道是怎么回事呀？我还专门用摄像机产生的信号和用FPGA生成的信号用示波器做过对比，没看到有差异，但是摄像机接到监视器上就没有上下抖动的现象。请各位指点迷境呀！！谢谢

liulanghan · 发表于 2010-3-30 11:16:45

与图象内容的数据无关，是时序信号不稳

litaoney · 发表于 2010-3-30 19:23:34

查一下资料，把行扫描和列扫描信号标准化。

logilas · 发表于 2010-4-1 23:08:19

最近查了下资料，主要是电视原理方面的书，发现书中对复合同步信号画的挺详细的，但是对于复合消隐信号确说的很模糊，不清楚复合消隐到底是个怎么样的时序和复合同步时个什么关系？？看书中只讲了场消隐持续时间为1600us+12us（行逆程），但是书上画的确是25个行周期，即1600us。同时书上介绍以场同步前均衡起始作为第一行，则从第23.5到310行，和从336到622.5行都是行数据有效期，其余时刻都为场消隐期，按照这个来算的话，2个场消隐加起来也只有50个行周期；如果算场消隐是在场同步前均衡起始处开始的，那么场消隐的起始就不会和行消隐的起始重合了~~~~
这几天开了半天真是百思不得其解呀，完全被书和资料弄混了，求大家帮帮忙看下我到底哪儿理解错了啊，道理复合同步和复合消隐是个什么样的关系呀？？小生跪谢了！！

wuquwuquwuqu · 发表于 2010-4-2 08:03:07

主要还是时序的问题吧？

ezhou98 · 发表于 2010-4-21 23:46:17

也关注一下

slq8966 · 发表于 2010-5-12 16:08:32

最近也在做这个我写了行场同步可是一点输出也没有？能看一下你写的时序吗？
可以的话发我邮箱slq8966@139.com 万分感谢我用AD723显示。

liulanghan · 发表于 2010-7-5 11:06:17

消隐信号不会引发图象抖动

HenryLai · 发表于 2010-7-5 15:33:01

查一下是不是 Even/Odd不一樣(X,Y)
或是LCD對Even/Odd的Vsync長度不一樣會發生.

oli · 发表于 2010-7-20 19:22:02

我也出现这种情况呀，
//project:blank_512_640
//function:generate the 7123's vsync using 7189's vs and fs.
//ok:?
//date:2010.04.21
module sync_blank_13p5(
//input
llc_13p5,
rst,

//vs_7189,
//fs_7189,
//sync,
//output
frame_count,
h_count,
v_count,

hblank,
vblank,
hv_sync,
hv_blank
);

/***********define io***************/
input llc_13p5;
input rst;
//input sync;

//output
//output[19:0]frame_count;//864*625=540000=0x83d60
output[19:0]frame_count;//864*625=540000=0x83d60
output[9:0]h_count;
output[9:0]v_count;
output hblank;
output vblank;
output hv_sync;
output hv_blank;

reg[19:0]frame_count;//864*625=540000=0x83d60
reg[9:0]h_count;
reg[9:0]v_count;
reg hblank;
reg vblank;
wire hv_sync;
wire hv_blank;
/************************************/

/***********define variable*********/
parameter ODD_BLANK_START=(20'd23+20'd16)*20'd864;
parameter ODD_BLANK_END=(20'd23+20'd16+20'd256)*20'd864;
parameter EVEN_BLANK_START=(20'd23+20'd16+20'd256+20'd15+20'd26+20'd16)*20'd864;
parameter EVEN_BLANK_END=(20'd23+20'd16+20'd256+20'd15+20'd26+20'd16+20'd256)*20'd864;

parameter ODD_SYNC_START=20'd0;//the data from the chart is 1 row,720
parameter EVEN_SYNC_START=20'd270000;//the data from the chart is 313 row,360

parameter US_32=9'd432;//32*13.5=432
parameter US_27P3=9'd368;//27.3*13.5=368.55
parameter US_2P35=5'd31;//2.35*13.5=31.725

reg[19:0]frame_count_temp;//864*625=540000=0x83d60
//reg[9:0]h_count;

reg vsync_flag;
reg hsync;
reg vsync;

//reg sync_old;
//reg sync_new;

/***********************************/

/************process start**********/
//process:1
//function:generate vf_old,vf_new
//process:2
//function:generate frame_count
/************process start**********/
//process:1
//function:generate sync_old,sync_new
/*always@(posedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
sync_old<=1'b0;
sync_new<=1'b0;
end
else
begin
sync_old<=sync_new;
sync_new<=sync;
end
end*/
//process:2
//function:generate frame_count
always@(negedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
frame_count_temp<=20'd0;
end
else
begin
case(frame_count_temp>=20'd539999)
1'b1:
frame_count_temp<=20'd0;
default:
frame_count_temp<=frame_count_temp+20'd1;
endcase
/*if({sync_old,sync_new}==2'b10)
begin
frame_count_temp<=20'd0;
end
else
begin
frame_count_temp<=frame_count_temp+20'd1;
end*/
end
end
always@(posedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
frame_count<=20'd0;
end
else
frame_count<=frame_count_temp;
end
//process:3
//function:generate h_count
always@(posedge llc_13p5 or negedge rst)
begin
if(!rst)
h_count<=10'd0;
else
h_count<=frame_count_temp%10'd864;
end
//process:4
//function:generate v_count
always@(posedge llc_13p5 or negedge rst)
begin
if(!rst)
v_count<=10'd1;
else
v_count<=frame_count_temp/10'd864+10'd1;
end
//process:5
//function:generate vblank
always@(negedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
vblank<=1'b0;
end
else
begin
case(frame_count)
ODD_BLANK_START:
vblank<=1'b1;
ODD_BLANK_END:
vblank<=1'b0;
EVEN_BLANK_START:
vblank<=1'b1;
EVEN_BLANK_END:
vblank<=1'b0;
default:;
endcase
end
end
//process:6
//function:generate hblank
always@(negedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
hblank<=1'b0;
end
else
begin
case(h_count)
10'd0:
hblank<=1'b0;
10'd184:
hblank<=1'b1;
10'd824:
hblank<=1'b0;
default:;
endcase
end
end
//process:7
//fuction:generate hv_blank
assign hv_blank=hblank&&vblank;
//process:5
//function:generate vsync
always@(negedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
vsync<=1'b1;
vsync_flag<=1'b0;
end
else
begin
case(frame_count)

20'd540000-US_32*5://forthward equalization start
begin
vsync_flag<=1'b1;
vsync<=1'b0;//forward equalization is start,is 5 period.1 period is 1 low,5 high
end
20'd540000-US_32*5+US_2P35:
vsync<=1'b1;
20'd540000-US_32*4://2 period start
vsync<=1'b0;
20'd540000-US_32*4+US_2P35:
vsync<=1'b1;
20'd540000-US_32*3://3 period start
vsync<=1'b0;
20'd540000-US_32*3+US_2P35:
vsync<=1'b1;
20'd540000-US_32*2://4 period start
vsync<=1'b0;
20'd540000-US_32*2+US_2P35:
vsync<=1'b1;
20'd540000-US_32://5 period start
vsync<=1'b0;
20'd540000-US_32+US_2P35:
vsync<=1'b1;

ODD_SYNC_START:
vsync<=1'b0;//  vsync is start;1 period is start,the low length is US_27P3
ODD_SYNC_START+US_27P3:
vsync<=1'b1;
ODD_SYNC_START+US_32:       //2 period is start
vsync<=1'b0;
ODD_SYNC_START+US_32+US_27P3:
vsync<=1'b1;
ODD_SYNC_START+US_32*2:       //3 period is start
vsync<=1'b0;
ODD_SYNC_START+US_32*2+US_27P3:
vsync<=1'b1;
ODD_SYNC_START+US_32*3:       //4 period is start
vsync<=1'b0;
ODD_SYNC_START+US_32*3+US_27P3:
vsync<=1'b1;
ODD_SYNC_START+US_32*4:       //5 period is start
vsync<=1'b0;
ODD_SYNC_START+US_32*4+US_27P3:
vsync<=1'b1;

ODD_SYNC_START+US_32*5:       //vsync is finished.backward is start
vsync<=1'b0;
ODD_SYNC_START+US_32*5+US_2P35:
vsync<=1'b1;
ODD_SYNC_START+US_32*6:       //2 period start
vsync<=1'b0;
ODD_SYNC_START+US_32*6+US_2P35:
vsync<=1'b1;//
ODD_SYNC_START+US_32*7:       //3 period start
vsync<=1'b0;
ODD_SYNC_START+US_32*7+US_2P35:
vsync<=1'b1;
ODD_SYNC_START+US_32*8:       //4 period start
vsync<=1'b0;
ODD_SYNC_START+US_32*8+US_2P35:
vsync<=1'b1;
ODD_SYNC_START+US_32*9:       //5 period start
vsync<=1'b0;
ODD_SYNC_START+US_32*9+US_2P35:
vsync<=1'b1;
ODD_SYNC_START+US_32*10:    //the backward is finished
begin
vsync_flag<=1'b0;
end
EVEN_SYNC_START-(US_32*6-US_2P35):
vsync_flag<=1'b1;
EVEN_SYNC_START-(US_32*5):
begin
vsync<=1'b0;
vsync_flag<=1'b1;
end
EVEN_SYNC_START-(US_32*5-US_2P35):
vsync<=1'b1;
EVEN_SYNC_START-(US_32*4):
vsync<=1'b0;
EVEN_SYNC_START-(US_32*4-US_2P35):
vsync<=1'b1;
EVEN_SYNC_START-(US_32*3):
vsync<=1'b0;
EVEN_SYNC_START-(US_32*3-US_2P35):
vsync<=1'b1;
EVEN_SYNC_START-(US_32*2):
vsync<=1'b0;
EVEN_SYNC_START-(US_32*2-US_2P35):
vsync<=1'b1;
EVEN_SYNC_START-(US_32):
vsync<=1'b0;
EVEN_SYNC_START-(US_32-US_2P35):
vsync<=1'b1;

EVEN_SYNC_START:
vsync<=1'b0;
EVEN_SYNC_START+US_27P3:
vsync<=1'b1;
EVEN_SYNC_START+US_32:
vsync<=1'b0;
EVEN_SYNC_START+US_32+US_27P3:
vsync<=1'b1;
EVEN_SYNC_START+US_32*2:
vsync<=1'b0;
EVEN_SYNC_START+US_32*2+US_27P3:
vsync<=1'b1;
EVEN_SYNC_START+US_32*3:
vsync<=1'b0;
EVEN_SYNC_START+US_32*3+US_27P3:
vsync<=1'b1;
EVEN_SYNC_START+US_32*4:
vsync<=1'b0;
EVEN_SYNC_START+US_32*4+US_27P3:
vsync<=1'b1;

EVEN_SYNC_START+US_32*5:
vsync<=1'b0;
EVEN_SYNC_START+US_32*5+US_2P35:
vsync<=1'b1;
EVEN_SYNC_START+US_32*6:
vsync<=1'b0;
EVEN_SYNC_START+US_32*6+US_2P35:
vsync<=1'b1;
EVEN_SYNC_START+US_32*7:
vsync<=1'b0;
EVEN_SYNC_START+US_32*7+US_2P35:
vsync<=1'b1;
EVEN_SYNC_START+US_32*8:
vsync<=1'b0;
EVEN_SYNC_START+US_32*8+US_2P35:
vsync<=1'b1;
EVEN_SYNC_START+US_32*9:
vsync<=1'b0;
EVEN_SYNC_START+US_32*9+US_2P35:
vsync<=1'b1;

EVEN_SYNC_START+US_32*10:
begin
vsync_flag<=1'b0;
end

default:;
endcase
end
end
//process:6
//function:generate hs
always@(negedge llc_13p5 or negedge rst)
begin
if(!rst)
begin
hsync<=1'b0;
end
else
begin
case(h_count)
10'd0:
hsync<=1'b0;
//10'd11:
//hsync<=1'b0;
10'd63:
hsync<=1'b1;
default:;
endcase
end
end
assign hv_sync=(hsync||vsync_flag)&&vsync;
endmodule

[求助] PAL制式显示FPGA实现问题

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