book for RTL designers

rocking_vlsi · 发表于 2017-12-21 01:04:11

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I am looking for books related systemverilog for design and verification. Can you please point me some books? If you have below one please please me also.

Rtl Modeling With Systemverilog for Simulation and Synthesis: Using Systemverilog for asic and FPGA Design

Thanks in advance

谁枫而飘 · 发表于 2017-12-23 19:42:05

回复 1# rocking_vlsi

please说中文

风中飞 · 发表于 2017-12-28 15:02:32

中文，xin'英文这么l好了，随便找本书

[讨论] book for RTL designers

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