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全球领先的电子设计服务供应商Cadence现招收正式员工啦。
工作地点：上海浦东嘉里中心/北京东城区北三环东路北京环球贸易中心
简历投递邮箱：marco3260@163.com 咨询：微信公众号留言（各种岗位都有，具体向我咨询） 标题：姓名+投递职位
详情请关注以下后端知识分享公众号：
后端
1. Principal Customer Engagement Engineer -Synthesis
Position Description: The primary responsibility is designing, developing, troubleshooting and debugging software programs on Unix/Linux platforms. Will be involved in developing software tools for advanced chip design platforms. The responsibilities also include engaging with customers in understanding their asic design requirements for nano-technology process nodes and assisting them in adopting Cadence design platform and helping them in performing successful tapeouts of their System-on-chip designs using the same. The job will also involves presenting and demonstrating relevant Cadence technologies and carrying out product evaluations, workshops, trainings and competitive replacement campaigns.
Position Requirements: The candidates should have strong in-depth RTL synthesis experience in COT or ASIC area. Experience and ability to get solutions in RTL Generic/Mapping as well as Phyiscal-aware synthesis is a MUST. Strong experience in timing analysis, sdc processing and understanding are also required. Need to have good knowledge on VDSM (40nm and below) processes issues. Good verbal and written presentation are must. Hands-on Cadence Synthesis experience will a big plus.
Minimum master degrees in EE or CS.
3. Product Engineer
Position Description: Work in shanghai Silicon Signoff and Verification (SSV) electrical PE team, focus on Voltus Power System (Voltus). Support key customer engagements and local AEs to help on the business increase. Working as a domain expert to well communicate with customers for their valuable feedbacks Co-work closely with R&D team to enhance the tool based on customers' real demanding
Position Requirements: Electrical analysis experience is necessary, IC level or system level power related analysis will be desired, e.g. Cadence Power System, Redhawk, Totem, Sigrity. Working experience with foundry and process tech files, spice models are desired Product Engineering and customer supporting experience is desired. Good communication in English and Chinese, good confidence and good self-motivation.
4. Principal Product Engineer
Position Description: We are looking for a dynamic individual to join the Cadence library characterization development group. This group is currently developing the best-in-class library characterization tools for standard cells, IO cells, memories and Analog / mixed signal macros. As a product engineer, you will shape our products and contribute to our market success. The product engineering team is the "voice of the customer" within the Characterization R&D group and is responsible for communication between R&D and sales, marketing, and application engineering as well as interfacing directly with major customers. You will define specifications for new characterization product features and help support advanced customer evaluations especially for new product roll-outs. You will work together with R&D on implementation and development of customer test suites. You will be responsible for reviewing product documentation, developing demonstrations and training as well as writing application notes and technical white papers.
Position Requirements: BS plus 5+ years’ experience in Library characterization with knowledge of Tcl, Shell Scripting (sh, csh, AWK etc.) and excellent communication skills. Detailed knowledge of Liberty Library data formats (NLM, CCS and ECSM) and transistor level (spice) simulation is required for this position. Familiarity with static timing analysis is desired. We prefer candidates with experience in: Transistor circuit simulation and analysis using Spectre, Finesim, and/or Hspice Memory simulation and analysis using Spectre_XPS, Finesim_Pro and/or XA Static timing, signal integrity and power analysis tools (Tempus/ETS/Voltus/PrimeTime/PT-PX), Standard cell, and IO/IP characterization and validation Digital Design Mixed signal design with knowledge of virtuoso ADE Design and simulation of large mixed signal blocks such as PLL, SERDES, DAC, ADC. Memory design and characterization Statistical variation simulation and modeling (Monte Carlo analysis) including LVF and AOCV | 
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发表于 2016-5-20 10:22:13
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