###################################### Current Design: TOP1553
# Load up design files
# uncomment one of the following
#analyze -format verilog TOP1553.v
analyze -format vhdl {if1553.vhd sysreg.vhd fifo.vhd transmitter.vhd rt1553.vhd receiver.vhd encode10m.vhd encode.vhd dpram.vhd decode10m.vhd decode.vhd TOP1553.vhd}
# Tell dc_shell the name of the top level module
elaborate TOP1553
# set a clock
create_clock {ext_clk clk}
# Check for warnings/errorsa
check_design -multiple_designs
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattened out
set_flatten true -effort high
uniquify
# compile the design
compile_ultra -area_high_effort_script
#compile_ultra -timing_high_effort_script
#compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
report_power
############################### begin: renaming section
# remove the following renaming section when not needed
# define the name rules for rename
define_name_rules verilog -remove_port_bus
define_name_rules verilog -remove_internal_net_bus
# name rule for nets
define_name_rules verilog -type net -allowed "a-z A-Z 0-9 _" \
-first_restricted "_ 0-9 N" \
-replacement_char "_" \
-prefix "n"