大型设计的仿真

1074048921

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cpri_tx_s_module is
end entity;

architecture rtl of cpri_tx_s_module is

    component cpri_tx_s_module is

port (
       --global signal

reset         
: in  std_logic;

speed_sel      
: in  std_logic_vector(1 downto 0);

pll_ref_clk   
: in  std_logic;


pulse_10ms
: in  std_logic;

pulse_10ms_tx

: out std_logic;

   tx_hdlc_rate          : in  std_logic_vector(2 downto 0);

--serdes

   ser_tx_k_A              : out std_logic_vector(1 downto 0);

   ser_txd_A               : out std_logic_vector(15 downto 0);

   ser_tx_k_B              : out std_logic_vector(1 downto 0);

   ser_txd_B               : out std_logic_vector(15 downto 0);

   ser_tx_k_C              : out std_logic_vector(1 downto 0);

   ser_txd_C               : out std_logic_vector(15 downto 0);

   ser_tx_k_D              : out std_logic_vector(1 downto 0);

   ser_txd_D               : out std_logic_vector(15 downto 0);



--send repeater serial number

repeater_serial_number
: in  std_logic_vector(31 downto 0);

--DELAY TUNE

parallel_compensate_value_A : in std_logic_vector(15 downto 0);

parallel_compensate_value_B : in std_logic_vector(15 downto 0);

parallel_compensate_value_C : in std_logic_vector(15 downto 0);

parallel_compensate_value_D : in std_logic_vector(15 downto 0);



--send carrier number

carrier_number_2_1  
: in  std_logic_vector(15 downto 0);

carrier_number_4_3  
: in  std_logic_vector(15 downto 0);

carrier_number_6_5  
: in  std_logic_vector(15 downto 0);

carrier_number_8_7  
: in  std_logic_vector(15 downto 0);

carrier_number_10_9
: in  std_logic_vector(15 downto 0);

carrier_number_12_11 : in  std_logic_vector(15 downto 0);


carrier_number_14_13 : in  std_logic_vector(15 downto 0);

carrier_number_16_15 : in  std_logic_vector(15 downto 0);



--lou delay count

frame_delay_cnt_local_A : in std_logic_vector(15 downto 0);

frame_delay_cnt_local_B : in std_logic_vector(15 downto 0);

frame_delay_cnt_local_C : in std_logic_vector(15 downto 0);

frame_delay_cnt_local_D : in std_logic_vector(15 downto 0);



--lou gain

lou_gain
: in  std_logic_vector(15 downto 0);

lou_power_input_dl
: in  std_logic_vector(15 downto 0);

phy_reset_indicate
: in std_logic_vector(7 downto 0);



--downlink_indicate

downlink_indicate_A
: in std_logic_vector(15 downto 0);


downlink_indicate_B
: in std_logic_vector(15 downto 0);


downlink_indicate_C
: in std_logic_vector(15 downto 0);


downlink_indicate_D
: in std_logic_vector(15 downto 0);


--hdlc
--
   hdlc_tx_data   
: in  std_logic;
--
   hdlc_tx_clk   
    : out std_logic;

tx_isk_eth
: in std_logic_vector(1 downto 0);

tx_data_eth
: in std_logic_vector(15 downto 0);

ethernet_tx_pulse
: out std_logic;

--iq

iq_tx_pulse_cpri_first_test : out std_logic;

iq_tx_pulse_first
: in  std_logic;

iq_tx_pulse_second
: in  std_logic;

tx_data_iq_first      : in  std_logic_vector(15 downto 0);

tx_data_iq_second     : in  std_logic_vector(15 downto 0)

);
    end component;




       --global signal

signal
reset         
:   std_logic:='0';

signal
speed_sel      
:   std_logic_vector(1 downto 0):="01";

signal
pll_ref_clk   
:   std_logic:='0';


signal
pulse_10ms
:   std_logic:='0';

signal
pulse_10ms_tx

:  std_logic;

signal   tx_hdlc_rate          :   std_logic_vector(2 downto 0):="001";

--serdes

signal  ser_tx_k_A              :  std_logic_vector(1 downto 0);

signal   ser_txd_A               :  std_logic_vector(15 downto 0);

signal   ser_tx_k_B              :  std_logic_vector(1 downto 0);

signal   ser_txd_B               :  std_logic_vector(15 downto 0);

signal   ser_tx_k_C              :  std_logic_vector(1 downto 0);

signal   ser_txd_C               :  std_logic_vector(15 downto 0);

signal   ser_tx_k_D              :  std_logic_vector(1 downto 0);

signal   ser_txd_D               :  std_logic_vector(15 downto 0);



--send repeater serial number

signal
repeater_serial_number
:   std_logic_vector(31 downto 0):=x"1111_1111";

--DELAY TUNE

signal
parallel_compensate_value_A :  std_logic_vector(15 downto 0):=x"0001";

signal
parallel_compensate_value_B :  std_logic_vector(15 downto 0):=x"0011";

signal
parallel_compensate_value_C :  std_logic_vector(15 downto 0):=x"0111";

signal
parallel_compensate_value_D :  std_logic_vector(15 downto 0):=x"1001";



--send carrier number

signal
carrier_number_2_1  
:   std_logic_vector(15 downto 0):=x"1111";

signal
carrier_number_4_3  
:   std_logic_vector(15 downto 0):=x"1011";

signal
carrier_number_6_5  
:   std_logic_vector(15 downto 0):=x"1110";

signal
carrier_number_8_7  
:   std_logic_vector(15 downto 0):=x"1011";

signal
carrier_number_10_9
:   std_logic_vector(15 downto 0):=x"1011";

signal
carrier_number_12_11 :   std_logic_vector(15 downto 0):=x"1111";


signal
carrier_number_14_13 :   std_logic_vector(15 downto 0):=x"1110";

signal
carrier_number_16_15 :   std_logic_vector(15 downto 0):=x"0111";



--lou delay count

signal
frame_delay_cnt_local_A :  std_logic_vector(15 downto 0):=x"4441";

signal
frame_delay_cnt_local_B :  std_logic_vector(15 downto 0):=x"5551";

signal
frame_delay_cnt_local_C :  std_logic_vector(15 downto 0):=x"6661";

signal
frame_delay_cnt_local_D :  std_logic_vector(15 downto 0):=x"7771";



--lou gain

signal
lou_gain
:   std_logic_vector(15 downto 0):=x"0001";

signal
lou_power_input_dl
:   std_logic_vector(15 downto 0):=x"0001";

signal
phy_reset_indicate
:  std_logic_vector(7 downto 0):=x"0001";



--downlink_indicate

signal
downlink_indicate_A
:  std_logic_vector(15 downto 0):=x"0001";


signal
downlink_indicate_B
:  std_logic_vector(15 downto 0):=x"0001";


signal
downlink_indicate_C
:  std_logic_vector(15 downto 0):=x"0001";


signal
downlink_indicate_D
:  std_logic_vector(15 downto 0):=x"0001";


--hdlc
--
   hdlc_tx_data   
: in  std_logic;
--
   hdlc_tx_clk   
    : out std_logic;

signal
tx_isk_eth
:  std_logic_vector(1 downto 0):=x"00";

signal
tx_data_eth
:  std_logic_vector(15 downto 0):=x"0000";

signal
ethernet_tx_pulse
:  std_logic;

--iq

signal
iq_tx_pulse_cpri_first_test :  std_logic;

signal
iq_tx_pulse_first
:   std_logic:='0';

signal
iq_tx_pulse_second
:   std_logic:='0';

signal
tx_data_iq_first      :   std_logic_vector(15 downto 0):=x"0000";

signal
tx_data_iq_second     :  std_logic_vector(15 downto 0):=x"0000";



-- Clock period definitions
    constant pll_ref_clk_period : time := 10 ns;





begin


   uut: cpri_tx_s_module

   PORT MAP (
          reset
=> logic_reset,
          speed_sel
=> "01",
          pll_ref_clk
=> global_clk,
          pulse_10ms
=> '0',

pulse_10ms_tx

=> pulse_10ms_tx,-- : out std_logic;
          tx_hdlc_rate
=> "011",

--serdes

ser_tx_k_A              =>
ser_tx_k_A,--
: out std_logic_vector(1 downto 0);

ser_txd_A               =>
ser_txd_A,--
: out std_logic_vector(15 downto 0);

ser_tx_k_B              =>
ser_tx_k_B,--
: out std_logic_vector(1 downto 0);

ser_txd_B               =>
ser_txd_B,--
: out std_logic_vector(15 downto 0);

ser_tx_k_C              =>
ser_tx_k_C,--
: out std_logic_vector(1 downto 0);

ser_txd_C               =>
ser_txd_C,--
: out std_logic_vector(15 downto 0);

ser_tx_k_D              =>
ser_tx_k_D,--
: out std_logic_vector(1 downto 0);

ser_txd_D               =>
ser_txd_D,--
: out std_logic_vector(15 downto 0);

--send repeater serial number

repeater_serial_number
=>
repeater_serial_number,--: in  std_logic_vector(31 downto 0);

--DELAY TUNE

parallel_compensate_value_A => parallel_compensate_value_A,--
: in std_logic_vector(15 downto 0);

parallel_compensate_value_B => parallel_compensate_value_B,--
: in std_logic_vector(15 downto 0);

parallel_compensate_value_C => parallel_compensate_value_C,--
: in std_logic_vector(15 downto 0);

parallel_compensate_value_D => parallel_compensate_value_D,--
: in std_logic_vector(15 downto 0);


--send carrier number

carrier_number_2_1      =>
carrier_number_2_1,

carrier_number_4_3      =>
carrier_number_4_3,

carrier_number_6_5      =>
carrier_number_6_5,

carrier_number_8_7      =>
carrier_number_8_7,

carrier_number_10_9     =>
carrier_number_10_9,

carrier_number_12_11    =>
carrier_number_12_11,

carrier_number_14_13    =>
carrier_number_14_13,

carrier_number_16_15    =>
carrier_number_16_15,



--lou delay count

frame_delay_cnt_local_A =>
frame_delay_cnt_local_A,--: in std_logic_vector(15 downto 0);

frame_delay_cnt_local_B =>
frame_delay_cnt_local_B,--: in std_logic_vector(15 downto 0);

frame_delay_cnt_local_C =>
frame_delay_cnt_local_C,--: in std_logic_vector(15 downto 0);

frame_delay_cnt_local_D =>
frame_delay_cnt_local_D,--: in std_logic_vector(15 downto 0);



--lou gain

lou_gain
=> lou_gain,--: in  std_logic_vector(15 downto 0);

lou_power_input_dl
=> lou_power_input_dl,--: in  std_logic_vector(15 downto 0);

phy_reset_indicate
=> phy_reset_indicate_tx,--: out std_logic_vector(7 downto 0);



--downlink_indicate

downlink_indicate_A
=> downlink_indicate_A,--: in std_logic_vector(15 downto 0);


downlink_indicate_B
=> downlink_indicate_B,--: in std_logic_vector(15 downto 0);


downlink_indicate_C
=> downlink_indicate_C,--: in std_logic_vector(15 downto 0);


downlink_indicate_D
=> downlink_indicate_D,--: in std_logic_vector(15 downto 0);


--
   
hdlc_tx_data   
=>  : in  std_logic;
--
   
hdlc_tx_clk   
   =>  : out std_logic;

tx_isk_eth
=>  tx_isk_eth,--: in std_logic_vector(1 downto 0);

tx_data_eth
=>  tx_data_eth,--: in std_logic_vector(15 downto 0);

ethernet_tx_pulse
=>  ethernet_tx_pulse,--: out std_logic;



iq_tx_pulse_cpri_first_test => iq_tx_pulse_cpri_first_test,--: out std_logic;
          iq_tx_pulse_first
=> iq_tx_pulse_out_first_i,
          iq_tx_pulse_second
=> iq_tx_pulse_out_second,
          tx_data_iq_first
=> tx_data_iq_out_first_i,--test_count,
          tx_data_iq_second
=> tx_data_iq_out_second--test_count
          );









signal
tx_data_iq_first      : in  std_logic_vector(15 downto 0):=x"0000";



signal
iq_tx_pulse_first
: in  std_logic:='0';



signal
tx_isk_eth
: in std_logic_vector(1 downto 0):=x"00";

signal
tx_data_eth
: in std_logic_vector(15 downto 0):=x"0000";





-- Clock process definitions
        pll_ref_clk_process :process
        begin

    pll_ref_clk <= '0';

    wait for pll_ref_clk_period/2;

    pll_ref_clk <= '1';

    wait for pll_ref_clk_period/2;
        end process;




    tb :process

begin

   wait for 10ns;

   pulse_10ms <= '1';

   wait for 10ns;

   wait for 6143990ns;

end process;


tb1 :process(pll_ref_clk)

begin

   tx_data_iq_first <=  tx_data_iq_first + '1';

end process;

DepravedLucien

高手兄，这是要干嘛啊

arlan122

testbench?