Verilog代码美化工具

hsdy · 发表于 2008-4-9 21:47:14

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Verilog代码美化工具,可以把我们写的杂乱的代码规整一下，对初学者尤其有用。

[ 本帖最后由 hsdy 于 2009-4-12 20:38 编辑 ]

hello0999 · 发表于 2008-4-11 15:31:29

有用吗？有用吗？

gutentag1 · 发表于 2008-4-11 17:25:20

有人用过吗？

seamas · 发表于 2008-7-9 22:08:44

试试看

szj112 · 发表于 2008-7-9 22:38:31

顶一个先

philio · 发表于 2008-7-12 19:33:40

:victory::victory::victory::victory:excellent,thanks in advance,excellent,thanks in advance,excellent,thanks in advance,

philio · 发表于 2008-7-12 19:45:46

:victory::victory::victory::victory:excellent,thanks in advance,excellent,thanks in advance,excellent,thanks in advance,

philio · 发表于 2008-7-12 20:01:25

:victory::victory::victory::victory:excellent,thanks in advance,excellent,thanks in advance,excellent,thanks in advance,

philio · 发表于 2008-7-12 20:05:58

:victory::victory::victory::victory:excellent,thanks in advance,excellent,thanks in advance,excellent,thanks in advance,

castro · 发表于 2008-7-12 20:28:22

貌似不错

excellent,thanks in advance,