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hardmany

帮忙下载这篇论文，谢谢。A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
Abstract:An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2 in 32nm CMOS SOI technology.



Published in: VLSI Circuits (VLSIC), 2013 Symposium on
Date of Conference: 12-14 June 2013
Date Added to IEEE Xplore: 16 August 2013
ISBN Information:


INSPEC Accession Number: 13711719
Publisher: IEEE
Conference Location: Kyoto, Japan

Chaumont

回复 1# hardmany
A 35mW8 b 8.8 GSs SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS.pdf (1.03 MB, 下载次数: 15 )

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hardmany

回复 2# Chaumont

thank you,Chaumont. Thanks a lot.

dcircuit

Thanks