【Synopsys武汉】招数字设计工程师（ARC subsystem）

synopsys_hire

Hi all,

这里是SynopsysHR，Qianyi，我们在武汉的研发中心招数字设计/验证相关职位，欢迎有兴趣的朋友发送联系方式到qyzhong@synopsys.com

Job title: ASIC digital design engineer
Location: Wuhan

We are a team working on producing IP subsystem products for the ARC family of 32-bit configurable processors.  The ARC processor family is among the leading embedded processor cores used world-wide . Synopsys is pioneering a new class of re-usable processor-based IP subsystems as a next step to increase overall SoC design productivity.  We are looking for an highly motivated and innovative digital design engineer like you to be part of the team to work on our world-class Processor-based IP subsystems that allow our customers develop highly optimized and very sophisticated embedded designs.


Key responsibilities
-        Develop and maintain IP subsystems including, specification, implementation and test.
-        Help in driving the innovation of processor-based  IP subsystems
-        Optimize designs for performance, speed, size and power
-        Interact with the verification, tools, modeling and simulation teams globally to deliver optimized solutions for our customers
-        Perform various benchmarking and engineering testing tasks to improve overall product quality
-        Keep abreast of state-of-the-art in Digital hardware Design methodology and tools
-        Guiding junior design engineers during product development

Required qualifications
-        Master degree (or equivalent) in Electrical or Computer Engineering with 5+ years of experience
-        Significant experience in digital hardware design including activities such as RTL development, functional simulation, constraint development, synthesis, timing analysis, power analysis, behavioral modeling, etc.
-        Experience / understanding of IC Design flows and good problem solving skills
-        Experience of Verilog design language.
-        A good understanding of the integration of digital hardware components such as peripherals, bus interconnect, processors and memories.
-        Good understanding of commonly used SoC interconnection protocols such as AMBA.
-        Experience with design  flow automation and scripting including Linux shell and Perl
-        Fluent In English, excellent communication skills

Our customers demand the highest quality design and verification and we need the right people to keep making this happen. As a worldwide organization there is occasionally short term travel required.

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zhangjiawen

校招招人不？急啊

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synopsys_hire

回复 4# zhangjiawen


    欢迎关注我们的公众微信号：新思科技招聘
校招相关信息参加公众微信号、大街网、应届生等相关网站。

zhangjiawen

回复 6# synopsys_hire

新思科技招聘，公众号一直关注着啊，总是看到社招的消息，就是没看到校招的消息。。。 武汉这边看来真的是只招社招啊。

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synopsys_hire

欢迎关注！

synopsys_hire

不错的机会，欢迎投递