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本帖最后由 spwedasd 于 2016-8-15 00:59 编辑
This book aims to fill in the gaps between computer vision and Verilog HDL design. For this purpose,
we have to learn about the four disciplines: Verilog HDL, vision principles, vision architectures, and
Verilog design. This area, which we call vision architecture, paves the way from vision algorithm to chip
design, and is defined by the related fields, the implementing devices, and the vision hierarchy.
In terms of related fields, vision architecture is a multidisciplinary research area, particularly related
to computer vision, computer architecture, and VLSI design. In computer vision, the typical goal of
the research is to design serial algorithms, often implemented in high-level programming languages and
rarely in dedicated chips. Unlike the well-established design flow from computer architecture to VLSI
design, the flow from vision algorithm to computer architecture, and further to VLSI chips, is not welldefined.
We overcome this difficulty by delineating the path between vision algorithm and VLSI design.
Vision architecture is implemented on many different devices, such as DSP, GPU, embedded processors,
FPGA, and ASICs. Unlike programming software, where the programming paradigm is more
or less homogeneous, designing and implementing hardware is highly heterogeneous in that different
devices require completely different expertise and design tools. We focus on Verilog HDL, one of the
representative languages for designing FPGA/ASICs.
The design of the vision architecture is highly dependent on the context and platform because the
computational structures tend to be very different, depending on the areas of study – image processing,
intermediate vision algorithms, and high-level vision algorithms – and on the specific algorithms used –
graph cuts, belief propagation, relaxation, inference, learning, one-pass algorithm, etc. This book is
dedicated to the intermediate vision, where reconstructing 3D information is the major goal.
This book by no means intends to deal with all the diverse topics in vision algorithms, vision
architectures, and devices. Moreover, it is not meant to report the best algorithms and architectures
for vision modules by way of extensive surveys. Instead, its aim is to present a homogeneous approach
to the design from algorithm to architecture via Verilog HDL, that guides the audience in extracting the
computational constructs, such as parallelism, iteration, and neighborhood computation, from a given
vision algorithm and interpreting them in Verilog HDL terms. It also aims to provide guidance on how
to design architectures in Verilog HDL so that the audience may be familiarized enough with vision
algorithm and HDL design to proceed to more advanced research.
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发表于 2016-8-14 00:39:02
发表于 2016-8-14 17:32:52
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