目前EOS有些什么行业测试标准呢？

ekc_maga

大概看了一下 只有JEDEC  ESDA的这部分标准比较全 但是系统实际情况还有很多特例 CDE目前没有标准 EOS是也没有标准吗？

公司的芯片设计的时候 会做哪些关于EOS的设计和测试呢？

ESDA-JEDEC  JS-001: ElectrostaticDischarge Sensitivity Testing -- HumanBody ModelThisStandard Test Method updates and revises an existing Standard. It establishes aprocedure for testing, evaluating and classifying the ESD sensitivity ofcomponents to the defined Human Body Model (HBM).

ANSI/ESD STM5.2): Electrostatic Discharge Sensitivity Testing -- Machine Model
This Standard establishes a test procedure for evaluating the ESD sensitivityof components to a defined Machine Model (MM).  The component damagecaused by the Machine Model is often similar to that caused by the Human BodyModel, but it occurs at a significantly lower voltage.

ANSI/ESD STM5.3.1: Electrostatic Discharge Sensitivity Testing - Charged Device Model -- Non-Socketed Mode
This Standard Test Method establishes a test method for evaluating the ESDsensitivity of active and passive components to a defined Charged Device Model(CDM).

ANSI/ESD SP5.3.2: Electrostatic Discharge Sensitivity Testing. – Socketed Device Method (SDM) –component Level.   
This standard practice provides a test method generating a Socketed DeviceModel (SDM) test on a component integrated circuit (IC) device.

ANSI/ESD SP5.4:  LatchupSensitivity Testing of CMOS/BiCMOS Integrated Circuits. – Transient LatchupTesting – Component Level Suppl Transient simulation.
This standard practice method was developed to instruct the reader on themethods and materials needed to perform Transient latchup testing.


ANSI/ESDSTM5.5.1:ElectrostaticDischarge Sensitivity Testing – TransmissionLine Pulse (TLP) – Component Level.

This document pertains to Transmission Line Pulse (TLP) testing techniques ofsemiconductor components. The purpose of this document is to establish amethodology for both testing and reporting information associated with TLP testing.

ANSI/ESD SP5.5.2:
ElectrostaticDischarge Sensitivity Testing - VeryFast Transmission Line Pulse (VF-TLP) - Component Level

This document pertains to Very Fast Transmission Line Pulse (VF-TLP) testingtechniques of semiconductor components.  It establishes guidelines andstandard practices presently used by development, research, and reliabilityengineers in both universities and industry for VF-TLP testing.  Thisdocument explains a methodology for both testing and reporting information associatedwith VF-TLP testing.

ANSI/ESD SP5.6:   ElectrostaticDischarge Sensitivity Testing - Human MetalModel (HMM) - Component Level

Establishes the procedure for testing, evaluating, and classifying the ESDsensitivity of components to the defined HMM.

jy02531779

目前我们都只会做ESD和latch-up，其他没做过

ekc_maga

回复 2# jy02531779


所以你们主要是HBM tester和Latch-up Tester？ TLP用得多吗？
Wei

jy02531779

回复 3# ekc_maga

不多，一般器件的TLP曲线代工厂都会提供，除非是自己设计的才会去测TLP。