有人能给我解释一下这段fft的verilog代码的问题吗

张小小06

//********************************************************************************
//移位处理单元模块
//*********************************************************************************
module shift_process(clk,rst,shift_in_valid,shift_ctrl,up_in_real,up_in_image,
                     dn_in_real,dn_in_image,
                                                        shift_out_valid,up_out_real,up_out_image,dn_out_real,
                                                        dn_out_image);

input clk,rst,shift_in_valid,shift_out_valid;
input shift_ctrl[1:0],
      up_in_real[11:0],up_in_image[11:0], dn_in_real[11:0],  dn_in_image[11:0];
                //分别是上一级和下一级RAM中的复数的实部和虚部输入
output up_out_real[9:0],up_out_image[9:0],dn_out_real[9:0],        dn_out_image[9:0];
       //分别是进行移位操作后的复数的实部和虚部输出

endmodule

编译过后
Error (10773): Verilog HDL error at shift_process.v(10): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
Error (10773): Verilog HDL error at shift_process.v(11): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions
Error (10773): Verilog HDL error at shift_process.v(13): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions

张小小06

手动顶

411123879

Yeah, you must know what packed arrays and unpacked arrays are. Packed arrays are something like this: input [1:0]shift_ctrl; while unpacked arrays are something like this: input shift_ctrl[1:0]. The difference is that when you index some bit like shift_ctrl[0], if you define shift_ctrl as a packed array, then shift_ctrl[0] is just a bit. However, if you define shift_ctrl as an unpacked array, then shift_ctrl[0] is just an int type which takes 4-8 bytes depending on your machine. So maybe in this case, you should use packed arrays.

张小小06

回复 3# 411123879


    谢谢，但还是会报错Error (10170): Verilog HDL syntax error at shift_process.v(11) near text "[";  expecting an identifier

张小小06

回复 3# 411123879


   

张小小06

回复 3# 411123879

改完之后报
    Error (10170): Verilog HDL syntax error at shift_process.v(11) near text "[";  expecting an identifier
Error (10170): Verilog HDL syntax error at shift_process.v(13) near text "[";  expecting an identifier
Error (10112): Ignored design unit "shift_process" at shift_process.v(4) due to previous errors

411123879

module shift_process(clk,rst,shift_in_valid,shift_ctrl,up_in_real,up_in_image,
                      dn_in_real,dn_in_image,
                                                         shift_out_valid,up_out_real,up_out_image,dn_out_real,
                                                         dn_out_image);

input clk,rst,shift_in_valid,shift_out_valid;
input [1:0]shift_ctrl;
input [11:0]up_in_real;
output [9:0]up_out_image;
output [9:0]dn_out_real;
output [9:0]dn_out_image;
        //分别是进行移位操作后的复数的实部和虚部输出

endmodule

Try this.

411123879

Or you could move input output identifiers into your module I/O list like this:

module arbiter(
    input clk,
    input req0,
    input req1,
    input rst,
    ouput gnt0,
    output gnt1
);

leopard520329

input shift_ctrl[1:0] :
改为input 【1:0】 shift_ctrl;

leopard520329

verilog 可综合的代码没有数组，只有数据位宽，在input 和端口名中间，并且其他的reg和wire型数据类型也类似，希望对你有帮助。