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楼主: hotraymanf

为什么spectre里面的vdsat不等于vgs-vth

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发表于 2008-9-26 21:39:29 | 显示全部楼层


同意,就算不同代工厂相同特征尺寸的工艺最优Vdast也不一样,具体可以把MOS特性曲线仿出来看看
发表于 2008-9-26 22:04:17 | 显示全部楼层
我也有同样的问题,现在学习了很多。
发表于 2008-9-30 14:28:17 | 显示全部楼层
这个问题困扰我好久了,这次受益良多
发表于 2008-10-30 20:28:38 | 显示全部楼层
关于这个问题,额也困惑了很久,大家都在积极参与讨论了,不过好像有不少回复都答非所问了,只有几个回复是对题的。

为什么Vdsat不等于Vgs-Vth,俺也死不明白,model的东西了解的太少了。

做个连接,在edaboard上有人问了这个问题,看了还是不甚明白。

如果你理解的透彻了,别忘了跟大家分享哈
http://www.edaboard.com/ftopic147151.html

http://www.edaboard.com/ftopic198286.html
发表于 2008-11-13 16:25:16 | 显示全部楼层
学习了不少,但还是不够透彻
发表于 2008-11-13 21:08:59 | 显示全部楼层
以前对这个问题也听模糊的,现在逐渐逐渐开始有一些理解,说一下自己的看法,不对的地方请指正:
以NMOS为例,NMOS管工作在饱和区的两个条件是:
Vgs>Vth1  
Vgd<Vth2  -> Vg-Vd<Vth2 -> -(Vg-Vd)>-Vth2

Vth1和Vth2的意义:是分别由源和漏的阈值电压
可以推出
Vds(sat)=Vds=Vd-Vs=(Vg-Vs)-(Vg-Vd)>Vgs-Vth2
可见,我们所求的Vdsat的阈值电压并不是由源决定的那个值,而是由漏决定的阈值电压(因为Vsb和Vdb的不同,源和漏两边的阈值电压实际是不同的,只是我们一般认为他们相同而已)
很明显对于一般的NMOS来说Vdb>Vsb,所以Vth1<Vth2,所以一般来说我们求得的Vdsat会比计算机仿真出来的大(当然Vth还与其他因素有关,这个结论并不绝对)
发表于 2008-11-14 13:40:05 | 显示全部楼层
vdsat考虑了衬偏效应
发表于 2015-12-13 17:22:25 | 显示全部楼层
借鉴别人的,没太明白:
Vov:过驱动电压overdrive voltage,Vov=Vgs-Vth,过驱动电压也用Vod表示
Vdsat:饱和漏源电压或夹断时漏源电压(刚出现夹断)saturation drain voltage
在长沟道下,vdsat=vgs-vth=vov,在短沟道下,由于二阶效应,vdsat小于vgs-vth,但这个值,spice也好,spectre也好,都是用来判断管子工作区间的。
vds>vdsat管子工作在饱和区
vds

Vov=Vgs-Vth,用MOS的Level 1 Model时,不考虑短沟道效用,Vdsat=Vov=Vgs-Vth,当Vds>Vdsat时,MOS的沟道就出现Pich-off现象,这时候电流开始饱和。(长沟道器件)

但是考虑到短沟道效应的模型里,沟道里的多子因为速度饱和效应(Velocity saturation),Vds不需要到达Vov,只要到达Vdsat,Ids就会饱和,不会再上升。但是此时在物理上,沟道并未达到Pinch- off,直到Vds=Vov,沟道的Pinch-off现象才会出现。也就是说在短沟道模型中,器件在沟道Pinch-off之前就会达到速度饱和,电流 不会再增加(短沟道器件)

Vds-Vdsat要留一定余量,一般200mv,差分输入对一般为100多mv,一般来说vdsat<50mV管子基本就工作在线性区;一是怕管子由于工艺进入线性区;二是饱和区边缘rds较小。

附英文解释:
Q:
We can see the parameter Vdsat in Cadence Spectre after we perform. the DC simulation. But I can't figure out what's the physical meaning of it?
I guess the vdsat is the overdrive voltage at first, but it's not exact the same as Vgs-Vth. The Vdsat is smaller than Vgs-Vth. So anyone has the idea what is Vdsat is the saturation drain voltage.

for a long channel device, Vdsat  almost equal to Vgs- Vth ( Vdsat = Vgs -Vth).
in strong inversion region(Vgs>Vth): NMOSFET works in linear region when 0<<Vgs -Vth ), the inversion channel behaves like a simple resistor. The drain current Ids increases linearly as the drain voltage Vds increases. However, when Vds is larger it will cause an increase of the voltage in the inversion layer at all points along the channel (except for the singular point at the source edge). This reduces the voltage across the gate capacitor and the inversion charge density is reduced. The smaller amount of mobile inversion charges results in a decrease in channel conductance, which leads to a smaller slope in the Ids -Vds characteristics as Vds increases. Eventually, Vds reaches the saturation voltage Vdsat , at which point the mobile carriers at the drain side disappear in this first order model, and the channel is "pinched off" at the drain side [2.4, 2.6]. The condition of no mobile carriers at the pinch-off point has traditionally been used to obtain the analytical saturation voltage expressions for long channel compact models.
NMOSFET works in  saturation region when VdsatVdsat, the pinched-off region of the channel increases and extends towards the source. The excess drain voltage beyond Vdsat will drop across this pinched-off region and the drain current remains approximately constant. However, we need to point out that the constant saturation current behavior. is only an approximation. The small but non-zero slope of the Ids -Vds characteristics in the saturation region is very important to analog circuit performance and must be accurately modeled by a compact model. In addition to the finite length of the pinch-off region (channel length modulation), drain induced barrier lowering and substrate current induced body effect must be accounted for in modeling the current in the saturation region.
for a short channel device, Vdsat = (Vgs -Vth)//(L*Esat)
so the device enters saturation before Vds reaches Vgs – Vth and operates more often in saturation.
critical gate voltage, at which an inversion layer is formed, is called the threshold voltage (Vth ).When the voltage between the gate and source, Vgs , is larger than Vth by several times the thermal voltage vt (KBT/q), the device is said to be in the strong inversion regime. When Vgs=Vdd (the power supply voltage), the device is in the “on” state. When Vgs is less than Vth , the device is in the subthreshold (or weak inversion) regime. When Vgs = 0, the device is in the “off” state. When Vgs is biased near Vth , the device operates in the moderate inversion egime,which is an important operation region in low power analog applications.
REFERENCE1. MOSFET Modeling and BSIM3 user's Guide, 1999
发表于 2015-12-19 16:41:21 | 显示全部楼层
学习学习
发表于 2016-4-13 09:58:25 | 显示全部楼层
回复 12# tjjbraye


    应该是看Vds与vod之间的比较吧
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