关于ISE的编译的一个错误198

mengyuwei290

新人求助！！！  综合可以，在implement时候，出现错误
Pack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx
   Answers database for "ERRORack:198" and read the Master Answer Record for
   MAP Trimming Issues.
这是什么问题啊！！！   我本来只是想试试DDS的ip核，下面是代码： 没有什么东西啊
module test_top(
    input clk_in,
    input rst_in
    );

wire [7:0] cosine;
(* KEEP="TRUE"*)wire [7:0] sine;
wire [15:0] phase_out;

DDS_test your_instance_name (
  .clk(clk_in), // input clk
  .sclr(rst_in), // input sclr
  .cosine(cosine), // output [15 : 0] cosine
  .sine(sine), // output [15 : 0] sine
  .phase_out(phase_out) // output [15 : 0] phase_out
);

endmodule

ucf文件：
# PlanAhead Generated miscellaneous constraints

NET "sine[0]" KEEP = "TRUE";
NET "sine[1]" KEEP = "TRUE";
NET "sine[2]" KEEP = "TRUE";
NET "sine[3]" KEEP = "TRUE";
NET "sine[4]" KEEP = "TRUE";
NET "sine[5]" KEEP = "TRUE";
NET "sine[6]" KEEP = "TRUE";
NET "sine[7]" KEEP = "TRUE";

# PlanAhead Generated physical constraints

NET "clk_in" LOC = V10;
NET "rst_in" LOC = P4;

# PlanAhead Generated IO constraints

NET "clk_in" IOSTANDARD = LVCMOS33;
NET "rst_in" IOSTANDARD = LVCMOS18;

mengyuwei290

为啥一直没人呢。。。

z894811350

UCF的问题

mengyuwei290

回复 3# z894811350

终于有人回我了。。。。    UCF啥问题啊    求解释！！！

z894811350

我也不是很了解，你把ucf里面的这些注释掉看看
NET "sine[0]" KEEP = "TRUE";
NET "sine[1]" KEEP = "TRUE";
NET "sine[2]" KEEP = "TRUE";
NET "sine[3]" KEEP = "TRUE";
NET "sine[4]" KEEP = "TRUE";
NET "sine[5]" KEEP = "TRUE";
NET "sine[6]" KEEP = "TRUE";
NET "sine[7]" KEEP = "TRUE";

mengyuwei290

回复 5# z894811350


    本来是用chipscope看的啊  我程序上也写了，我也试过把它注释掉，但还是报错

z894811350

我也建了一个工程，加入一个输出的io吧，然后就可以了

mengyuwei290

回复 7# z894811350

要加个输出？。。。这个为啥呢？   本来就是仿真chipscope看一下啊  要不我把sine弄成输出？

z894811350

这个我也不知道为啥，但是我跟你出现同样的问题，加了一个输出测试引脚就可以了。
(
    input    wire    clk_in,
    input    wire    rst_in,
         output   wire    test_io
);

(* KEEP="TRUE"*)wire [5:0] cosine;
(* KEEP="TRUE"*)wire [5:0] sine;
(* KEEP="TRUE"*)wire [26:0] phase_out;

wire    clk_100M;

assign    test_io = sine[0]&cosine[0];

BUFG BUFG_inst
(
      .O(clk_100M), // 1-bit output: Clock buffer output
      .I(clk_in)  // 1-bit input: Clock buffer input
);

DDS_IP your_instance_name
(
  .clk(clk_100M), //
  .sclr(rst_in), //
  .cosine(cosine), //
  .sine(sine), //
  .phase_out(phase_out) //
);
NET "clk_in"             LOC = T8  |IOSTANDARD = LVCMOS33 ;
NET "rst_in"             LOC = M12 |IOSTANDARD = LVCMOS33 ;
NET "test_io"            LOC = L10 |IOSTANDARD = LVCMOS33 ;
我这样做的，可以顺利通过

mengyuwei290

回复 9# z894811350


    我去试试去，先谢谢了，好心人。。。