VARIABLE POWER_NAME "?VDD?" "?vdd?"
VARIABLE GROUND_NAME "?VSS?" "?GND?" "?vss?" "?gnd?"
LVS POWER NAME POWER_NAME
LVS GROUND NAME GROUND_NAME
LVS RECOGNIZE GATES NONE
VIRTUAL CONNECT COLON NO
LVS ABORT ON SOFTCHK NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE YES
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS CELL SUPPLY NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS REDUCE SPLIT GATES NO ///###change add this for check same nodes missing net.20150624
LVS SPICE REPLICATE DEVICES YES ///###change add this for check same nodes missing net.20150624
LVS REDUCE PARALLEL MOS NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LVS DOWNCASE DEVICE NO
LVS REPORT OPTION A
//VIRTUAL CONNECT NAME "?VDD?" "?VSS?" "?GND?" "?vdd?" "?vss?" "?gnd?"
//LVS FILTER UNUSED OPTION AB RC RE RG YC
LVS REDUCE SPLIT GATES NO ///###change add this for check same nodes missing net.20150624
LVS SPICE REPLICATE DEVICES YES ///###change add this for check same nodes missing net.20150624
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS NO