set hdlin_no_group_register TRUE
set enable_recovery_removal_arcs TRUE
set power_preserve_rtl_hier_names TRUE
set power_hdlc_do_not_split_cg_cells TRUE
set power_do_not_size_icg_cells FALSE
set compile_new_optimization TRUE
set compile_seqmap_propagate_constants FALSE
set timing_non_unate_clock_compatibility TRUE
set compile_delete_unloaded_sequential_cells TRUE
set compile_ultra_ungroup_dw TRUE
set high_fanout_net_pin_capacitance 0
set case_analysis_with_logic_constants TRUE
set timing_input_port_default_clock FALSE