我写了个比较器想试用一下synplify，但是状态是Done（error），不知道怎么回事

水泥

小白不懂，望各位大神赐教！

wangshikun118

代码发上来瞧瞧啊，光看这能看出啥

guofu2010

好歹看下编译的报告啊

水泥

回复 2# wangshikun118

module compare(equal,a,b);
input a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule
额，这是代码，我就想试试这个软件怎么用...是不是哪里配置有问题呢？谢谢！

水泥

回复 3# guofu2010


   #Build: Synplify Pro H-2013.03, Build 120R, Feb 24 2012#install: F:\synpilfy\fpga_H201303
#OS: Windows 7 6.1
#Hostname: 123-PC


#Implementation: rev_3


$ Start of Compile
#Sun Jan 18 13:55:17 2015


Synopsys Verilog Compiler, version comp201303rc, Build 045R, built Feb 28 2013
@N: :  | Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.


@N: :  | : Running Verilog Compiler in System Verilog mode
@N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode
@I::"F:\synpilfy\fpga_H201303\lib\altera\altera.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\cycloneive.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_mf.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_lpm.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_primitives.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\umr_capim.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\scemi_objects.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\scemi_pipes.svh"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\hypermods.v"
@I::"E:\FPGAstudy\compare\compare.v"
Verilog syntax check successful!
Selecting top level module compare
@N:CG364 : compare.v(1) | Synthesizing module compare


@END


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)


Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 18 13:55:18 2015


###########################################################]
小白表示不懂啊，大神帮忙看看。谢谢！

guofu2010

你的代码没有什么问题，可能软件有问题，你把综合目录下的.srr文件发过来

guofu2010

如果只是想学习的话，Synplify安装目录下的手册看看，里面就有许多例子。

水泥

回复 6# guofu2010
ok

   #Build: Synplify Pro H-2013.03, Build 120R, Feb 24 2012#install: F:\synpilfy\fpga_H201303
#OS: Windows 7 6.1
#Hostname: 123-PC


#Implementation: rev_3


$ Start of Compile
#Sun Jan 18 13:55:17 2015


Synopsys Verilog Compiler, version comp201303rc, Build 045R, built Feb 28 2013
@N: :  | Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.


@N: :  | : Running Verilog Compiler in System Verilog mode
@N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode
@I::"F:\synpilfy\fpga_H201303\lib\altera\altera.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\cycloneive.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_mf.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_lpm.v"
@I::"F:\synpilfy\fpga_H201303\lib\altera\quartus_II121\altera_primitives.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\umr_capim.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\scemi_objects.v"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\scemi_pipes.svh"
@I::"F:\synpilfy\fpga_H201303\lib\vlog\hypermods.v"
@I::"E:\FPGAstudy\compare\compare.v"
Verilog syntax check successful!
Selecting top level module compare
@N:CG364 : compare.v(1) | Synthesizing module compare


@END


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)


Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 18 13:55:18 2015


###########################################################]
这是报告..

水泥

回复 7# guofu2010


    compare.docx (12.07 KB, 下载次数: 3 )

2015-1-18 14:06 上传

点击文件名下载附件

我直接复制过来，貌似一直在审核....帮忙看看，谢谢！

haochen111

好好好好