muer小数pll频率合成器经典教材CMOS_Fractional-N_Synthesizers.Design

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CMOS_Fractional-N_Synthesizers.Design_for_High_Spectral_Purity_and_Monolithic_Integration

非扫描版！！！
除了基本pll理论，该书还包括很多工程细节，尤其是电路方面，讲的非常细。是一本很好的关于fraction-N pll的教材

1  Introduction  1  
1.1  Telecommunications: An Overview  1  
1.2 Telecommunications: A Market Perception  3  
1.3 Integration: Why, How and In What?  4  
1.3.1  P-Words  5  
1.3.2  Direct Conversion Transceivers  6  
1.3.3  CMOS Technology  7  
1.3.4  Trends in Research Evolution  8  
1.4 The Research Book  9  
1.5  The Outline of the Book  11  
2  On Frequency Synthesis  13  
2.1 Introduction  13  
2.2 Indirect or Phase-Locked Loop Frequency Synthesizers  14  
2.2.1  Phase-Lock  14  
2.2.2  Phase-Lock Frequency Synthesis Fundamentals  16  
2.3 The Synthesizer Data Sheet  17  
2.3.1  Spectral Purity  17  
2.3.1.1  Definition of Phase Noise  17  
2.3.1.2  Phase Noise in a PLL  20  
2.3.1.3  rms Phase Error  22  
2.3.1.4  Spurious Suppression  23  
2.3.2  Loop Dynamics  23  
2.3.2.1  Tracking and Settling  23  
2.3.2.2  Acquisition  24  
2.3.3  Other Specifications  25  
2.4 Introduction to PLL building blocks  25  
2.4.1  The Phase Detector  25  
2.4.1.1 Analog Phase Detectors 25
2.4.1.2 The EXOR Phase Detector 26
2.4.1.3 Flipflop Phase Detectors 26
2.4.1.4 The Phase-Frequency Detector 27
2.4.2 The Loop Filter 29
2.4.2.1 Second-Order PLLs 29
2.4.2.2 Third-Order PLLs 33

2.4.3 The Oscillator 33
2.4.3.1 The Xtal Oscillator 34
2.4.3.2 The Relaxation Oscillator 35
2.4.3.3 The Ring Oscillator 35
2.4.3.4 The LC Oscillator 36
2.4.3.5 Other Oscillator Types 36

2.4.4 The Frequency Divider 36
2.4.4.1 Programmable Dividers 37
2.5 Advanced PLL Frequency Synthesizers 38
2.5.1 Combining Frequency Synthesizers 39
2.5.2 Fractional-N Frequency Synthesizers 40

2.6 Frequency Synthesis for the DCS-1800 System 41
2.6.1 A Fully Integrated DCS-1800 Transceiver 41
2.6.2 The DCS-1800 Communication System 43
2.6.3 From DCS-1800 to Synthesizer Specifications 44
2.6.3.1 From Bit-error Rate to Signal-to-Noise Ratio 44
2.6.3.2 Phase Noise 46
2.6.3.3 Spurious Suppression 46
2.6.3.4 rms Phase Error 48
2.6.3.5 Dynamic Performance 49
2.6.3.6 Specification Summary 50

2.7 Conclusion 50
3 High-Speed CMOS Prescalers 53
3.1 Introduction 53
3.2 The Phase-Switching Dual-Modulus Prescaler 54
3.2.1 Conventional Architecture 54
3.2.2 The Phase-Switching Architecture 56

3.3 A Single-Ended 1.5 GHz 8/9 Dual-Modulus Prescaler in
CMOS 58
3.3.1 The High-Speed Divide-by-2 D-flipflop 58
3.3.2 The Half-speed Divide-by-2 D-flipflop 60
3.3.3 Phase Noise Considerations 61
3.3.4 Experimental Results 63
3.3.4.1 General Results 63
3.3.4.2 Phase Noise Results 65
3.3.4.3 Design Issue: The Quadrature Accuracy 67
3.4 A Single-ended 1.8 GHz 8/9 DMP in
“Radiation Hardened” BiCMOS
67
3.4.1  The Circuit Implementation 67
3.4.2  Experimental Results 70

3.5 A 1.8 GHz 16-modulus /64-/79 Prescaler in
CMOS  71
3.5.1  The Divide-by-2 Flipflops 71
3.5.2  The Multi-Modulus Implementation 73
3.5.3  Experimental Results 74

3.6 A 12 GHz /128 Prescaler in
CMOS  75
3.6.1  Introduction 75
3.6.2  The Circuit Implementation 76
3.6.2.1 The High-Speed Divide-by-2 Flipflop  76
3.6.2.2 The Divide-by-128 Prescaler  77
3.6.2.3 The Input Section  78

3.6.3  Experimental Results 79

3.7 Conclusion  82
4 Monolithic CMOS LC-VCOs  85
4.1 Introduction  85
4.2 General Oscillator Theory  86
4.3 A Design-Oriented Non-Linear Phase Noise Theory  88
4.3.1  The Theory 88
4.3.1.1 Modeling of the Non-linear Active Element  88
4.3.1.2 Phase Noise Analysis  90

4.3.2  Comparison with Other Published Theories 93

4.4 Integrated LC-tanks in CMOS  95
4.4.1  Introduction 95
4.4.2  Integrated Planar Inductors in Standard CMOS 96
4.4.2.1 First Order Planar Inductor Model  96
4.4.2.2 Losses in Integrated Planar Inductors  97
4.4.2.3 The Simulator-Optimizer  101
4.4.2.4 The Balanced Octagonal Inductor and Its Model 103

4.4.3  Integrated Varactors in Standard CMOS 105

4.5 The VCO Circuit Design  107
4.5.1  General VCO Circuit Design 107
4.5.2  Bipolar or CMOS? 109
4.5.3  The Power Efficiency of VCO Circuits 110
4.5.3.1 Hand Calculation MOS Model  110
4.5.3.2 Complementary MOS or xMOS-only VCO?  112
4.5.3.3 NMOS-only or PMOS-only VCO?  113
Phase Noise Mechanisms and Minimization  1134.5.4

4.6 Implementations  116
4.6.1  A 2 GHz Low-Phase-Noise LC-VCO Set with Flicker Noise Minimiza-tion in
(Bi)CMOS  116
4.6.1.1  Inductor Design 116
4.6.1.2  VCO Design with Flicker Noise Minimizaion 118
4.6.1.3  Experimental Results 120
4.6.1.4  Extremely Low-Phase-Noise Measurement at 2.02 GHz: -132.5 dBc/Hz at 600 kHz and No Flicker Noise Upconversion !! 123



4.6.2 A 1.8 GHz Highly-Tunable Low-Phase-Noise VCO in
CMOS
125
4.6.2.1  Inductor Design 125
4.6.2.2  VCO Design 125
4.6.2.3  Experimental Results 128
4.6.2.4  Quadrature Operation 129
4.7 Comparison with Published State-of-the-Art VCOs  130
4.8 Conclusion  133
5 Monolithic Phase-Locked Loops  137
5.1 Introduction  137
5.2 Loop Filter Topology Selection  138
5.2.1 Charge Pump PLL  139
5.2.2 Fourth-Order PLL  141

5.3 Dual-Path Fourth-Order PLL  142
5.3.1 Dual-Path Filter Topology  143
5.3.2 Transfer Functions  144
5.3.2.1  Open Loop Gain 144
5.3.2.2  Charge Pump Noise 145
5.3.2.3  Loop Filter Noise 146

5.3.3 Filter Optimization  147
5.3.4 Conventional Versus Dual-Path Topologies  152

5.4 The PLL Building Block Circuits  153
5.4.1 The 3-step Equalizer Circuit  153
5.4.2 The Loop Filter Circuit  155

5.5 Experimental Results  156
5.6 Conclusion  161
6 A 1.8 GHzCMOS
Fractional-N Frequency Synthesizer  163
6.1 Introduction  163
6.2 The Fractional-N Principle  164
6.3 Conventional Fractional Compensation Methods  167
6.3.1 The Analog Phase Interpolator  167
6.3.2 The Fractional Divider  168
6.4
Modulation in Fractional-N Synthesis  169
6.4.1 Introduction  169
6.4.2 The Accumulator as Noise-Shaping Quantizer  169
6.4.3 General
Modulator Theory  170
Modulators with DC-inputs  1726.4.4
6.5
Modulators for Fractional-N Synthesis
6.5.1 The MASH Modulator
6.5.2 The Multi-Bit, Single-Loop
Modulator

6.6 The Theoretical
Phase Noise Analysis
6.6.1 The Out-of-Band
Phase Noise
6.6.2 The
rms Phase Error

6.7 A Fast Non-Linear
Phase Noise Analysis Method
6.7.1 The Analysis Method
6.7.2 Analysis Results
6.7.3 Analysis Results: The Origin of Spurious Tones

6.8 The Fractional-N Synthesizer Circuit Design
6.8.1 The Phase-Frequency Detector
6.8.2 The Charge Pumps
6.8.2.1 The Spurious Suppression
6.8.2.2 The Gain Mismatch
173 174 175 178 179 183 185 186 189 195 197 198 200 201 204

6.9 Experimental Results 205
6.9.1 Measurement Setup 205
6.9.2 Measurement Results 207
6.9.3 Comparison with Published
Fractional-N Synthesizers 215

6.10 Conclusion 218
7 Conclusions 221
7.1 A 2V CMOS Cellular Transceiver Front-End 221
7.2 Main Contributions and Achievements 225
7.3 Epilogue 227

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part 4-6

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part 7-9

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part10-12

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part13-part15

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终于传完了！！！！

wangjin0215

luguo

smaa

thx a lot

smaa

thx a lot

smaa

thx a lot