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初学verilog,在modelsim里编译成功的程序为什么在quartus里编译显示错误呢?module mux_two(out,a,b,sl);
input a,b;
input sl;
output out;
reg out;
always @(a or b or sl)
if(!sl==1)
out=a;
else
out=b;
endmodule
提示:
Error (287076): Can't find an inherited or default value for parameter "WIDTH" -- specify a parameter value
Error (287072): Symbolic name "WIDTH" is used but not defined
Error (287037): Argument for LOG2 cannot be negative number or zero
Error (287087): Group range of arithmetic expression contains negative number -1, but numbers in group ranges cannot be negative
Error (287087): Group range of arithmetic expression contains negative number -1, but numbers in group ranges cannot be negative
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings
Error: Peak virtual memory: 347 megabytes
Error: Processing ended: Tue Oct 21 22:12:49 2014
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 0 warnings |
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