【电子书】nanometer CMOS ICs

gellmann · 发表于 2014-8-21 22:10:49

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Foreword
Preface
Overview of symb ols
List of physical constants

1 Ba sic P rinciples 1
1.1 Introduct ion . ....... . .... . 1
1.2 The field-effect prin ciple . . . . . . . 1
1.3 The inversion-layer MaS transisto r . 4
1.3.1 The Metal-Oxide-Semiconducto r (MaS) capacitor 11
1.3.2 The inversion-layer Ma S t rans istor " 15
1.4 Derivation of simple Ma S formulae. . . . . . . . . . . . . 23
1.5 The back-bias effect (back-gate effect, body effect) and
the effect of forward-bias " 27
1.6 Factors which characterise t he behaviour of the MaS transistor.
. . . . . . . . . . . . . . . . 30
1.7 Different typ es of MaS transistors 32
1.8 Parasitic MaS tr ansistors . . . . 34
1.9 MaS transistor symbols . . . . . 36
1.10 Capacitances in MaS structures 38
1.11 Conclusions 48
1.12 References . 49
1.13 Exercises . 50
2 Geometrical-, physi cal- and field-scaling impact on MOS
t r ansist or behaviour 57
2.1 Introduction . .. . . . . .... . .. . . . . . . . . . . . . 57
2.2 The zero field mobili ty . . . . . . . 58
2.3 Carrier mobili ty reduction. .. 59
2.3.1 Vertical and lat eral field carrier mobility reduction 59
2.3.2 St ress-induced carrier mobility effects 63
2.4 Channel length modulation 64
2.5 Short- and narrow-channel effects . 66
2.5.1 Short-channel effects . 66
2.5.2 Narrow-channel effect 69
2.6 Temperature influence on carrier mobility and threshold
voltage . 71
2.7 MaS transist or leakage mechanisms 74
2.7.1 Weak-inversion (subthreshold ) behaviour of the
MaS transistor . 75
2.7.2 Gate-oxide tunnelling 78
2.7.3 Reverse-bias junction leakage 80
2.7.4 Gate-induced dr ain leakage (GIDL) 81
2.7.5 Impact Ionisation . 82
2.7.6 Overall leakage int eractions and considerations 83
2.8 MaS transistor models . 86
2.9 Conclusions 88
2.10 References . 89
2.11 Exercises 91
3 Manufacture of MOS devices 93
3.1 Int roduct ion. ... . . . . . . .. .. . ... ... 93
3.2 Different substrates (wafers) as starting material 95
3.2.1 Wafer sizes . . . . . . . . . . . . . . . . . 95
3.2.2 Standard CMOS Epi . . . . . . . . . . . . 95
3.2.3 Cryst alline orientation of the silicon wafer 98
3.2.4 Silicon-on-insulator (Sal) 99
3.3 Lithography in MaS processes . ... . . . . . . 105
3.3.1 Lit hography basics . . . . . . . . . . . . . 105
3.3.2 Lithographic alte rn at ives beyond 40 nm . 121
3.3.3 Next generation lithography. . . . . . . . 124
3.3.4 Mask cost reduct ion techniques for low-volume production
. 126
3.4 Etching . . . 131
3.5 Oxidation . . . . 134
3.6 Deposition . .. . 137
3.7 Diffusion and ion implant ation . 142
3.8 Planarisation . . . . . . . . . . . . . . . . . . . 146
3.9 Basic MOS technologies . . . . . . . . . . . . . 153
3.9.1 The basic silicon-gate nMOS process. . 153
3.9.2 The basic Complementary MOS (CMOS) process. 158
3.9.3 An advanced nanometer CMOS process . . 160
3.9.4 CMOS technology options beyond 45nm . . 168
3.10 Conclusions . 178
3.11 References . . 179
3.12 Exercises . . 183
4 CMOS circuits 185
4.1 Introduction... ..... . 185
4.2 The basic nMOS inverter . 186
4.2.1 Introduction . .. . 186
4.2.2 The DC behaviour . 188
4.2.3 Comparison of the different nMOS inverters . . 196
4.2.4 Transforming a logic function into an nMOS transistor
circuit . 197
4.3 Electrical design of CMOS circuits . 200
4.3.1 Introduction . ... . 200
4.3.2 The CMOS inverter . 201
4.4 Digital CMOS circuits . . . . 218
4.4.1 Introduction .... . 218
4.4.2 Static CMOS circuits . 219
4.4.3 Clocked static CMOS circuits . . 225
4.4.4 Dynamic CMOS circuits . . . . . 228
4.4.5 Other types of CMOS circuits. . 234
4.4.6 Choosing a CMOS implementation . 235
4.4.7 Clocking strategies . . . . . . . . . 236
4.5 CMOS input and output (I/O) circuits. . 237
4.5.1 CMOS input circuits. . . . . . . 237
4.5.2 CMOS output buffers (drivers) . 238
4.6 The layout process . . . . . . 240
4.6.1 Introduction . ... . 240
4.6.2 Layout design rules. . 241
4.6.3 Stick diagram . . . . . 245
4.6.4 Example of the layout procedure . 248
4.6.5 Guidelines for layout design . 252
4.7 Conclusions . 254
4.8 References ... .. .. . 255
4.9 Exercises . . 257
5 Special circuits, devices and technologies 261
5.1 Introduction .. .. . . . .... . 261
5.2 CCD and CMOS image sensors . 262
5.2.1 Introduction . . . . . . 262
5.2.2 Basic CCD operation . 262
5.2.3 CMOS image sensors . . 267
5.3 Power MOSFET transistors . . 270
5.3.1 Introduction .. ... . 270
5.3.2 Technology and operation . 271
5.3.3 Applications .. . 274
5.4 BICMOS digital circuits . . . 275
5.4.1 Introduction .. .. . 275
5.4.2 BICMOS technology . 276
5.4.3 BIGMOS characteristics . 279
5.4.4 BICMOS circuit performance . 280
5.4.5 Future expectations and market trends. . 283
5.5 Conclusions . 284
5.6 References. . 285
5.7 Exercises . 287
6 Memories 289
6.1 Introduction .. . .... ... ..... . 289
6.2 Serial memories . . . . . . . . . . . . . . 293
6.3 Content-addressable memories (CAM) . 294
6.4 Random-access memories (RAM) . 294
6.4.1 Introduction . 294
6.4.2 Static RAMs (SRAM) . . . 294
6.4.3 Dynamic RAMs (DRAM) . 310
6.4.4 High-performance DRAMs . 321
6.4.5 Single- and dual port memories . 327
6.4.6 Error sensitivity . 328
6.4.7 Redundancy .. . 328
6.5 Non-volatile memories . 329
6.5.1 Introduction .. . 329
6.5.2 Read-Only Memories (ROM) . 329
6.5.3 Programmable Read-Only Memories . 334
6.5.4 EEPROMs and flash memories . 337
6.5.5 Non-volatile RAM (NVRAM) . . 345
6.5.6 BRAM (battery RAM) . 346
6.5.7 FRAM, MRAM, PRAM (PCM) and RRAM . 346
6.6 Embedded memories . . . . . . . . . . . 350
6.7 Classification of the various memories . 353
6.8 Conclusions . 355
6.9 References. . 357
6.10 Exercises . . 362
7 Very Large Scale Integration (VLSI) and ASICs 365
7.1 Introduction ... ...... . 365
7.2 Digital ICs . 368
7.3 Abstraction levels for VLSI . 373
7.3.1 Introduction . . . 373
7.3.2 System level . . . . 376
7.3.3 Functional level . . 379
7.3.4 RTL level . . . . . 380
7.3.5 Logic-gate level . . 383
7.3.6 Transistor level . 384
7.3.7 Layout level. . 386
7.3.8 Conclusions. . 386
7.4 Digital VLSI design . 389
7.4.1 Introduction . 389
7.4.2 The design trajectory and flow . 389
7.4.3 Example of synthesis from VHDL description to
layout . . . . . . . . . . . . . . . 394
7.5 The use of ASICs . . . . . . . . . . . . . 402
7.6 Silicon realisation of VLSI and ASICs . 403
7.6.1 Introduction . 403
7.6.2 Handcrafted layout implementation . 406
7.6.3 Bit-slice layout implementation . . . . 407
7.6.4 ROM, PAL and PLA layout implementations . 408
7.6.5 Cell-based layout implementation. . . . . . 413
7.6.6 (Mask programmable) gate array layout implementation
. . . . . . . . . . . . . . . . . . . . . . . 415
7.6.7 Programmable Logic Devices (PLDs) 420
7.6.8 Embedded Arrays, Structured ASICs and platform
ASICs . . . . . . . . . . . . . . . . . . . . 434
7.6.9 Hierarchical design approach . 438
7.6.10 The choice of a layout implementation form . 439
7.7 Conclusions. .. . .. . . . . . . . . . . . . . . 443
7.8 References .
7.9 Exercises .
8 Low power, a hot topic in IC design 447
8.1 Introduction.............. . 447
8.2 Battery technology summary . . . . . 448
8.3 Sources of CMOS power consumption . 450
8.4 Technology options for low power . . . . 452
8.4.1 Reduction of l1eak by technological measures . 452
8.4.2 Reduction of Pdyn by technology measures . . . 457
8.4.3 Reduction of Pdyn by reduced-voltage processes . 459
8.5 Design options for power reduction . . . . . . . . . . . . 462
8.5.1 Reduction of Pshort by design measures . . . . . . 462
8.5.2 Reduction/elimination of Pstat by design measures 464
8.5.3 Reduction of P dyn by design measures 465
8.6 Computing power versus chip power, a scaling perspective 501
8.7 Conclusions . 504
8.8 References. . 505
8.9 Exercises . . 509
9 Robustness of nanometer CMOS designs: signal integrity,
variability and reliability 511
9.1 Introduction 511
9.2 Clock generation, clock distribution and critical timing. . 513
9.2.1 Introduction 513
9.2.2 Clock distribution and critical timing issues 514
9.2.3 Clock generation and synchronisation in different
(clock) domains on a chip .....
9.3 Signal integrity . . . . . . . . . . . . . . . . . . .
9.3.1 Cross-talk and signal propagation .... .
9.3.2 Power integrity, supply an ground bounce
9.3.3 Substrate bounce .
9.3.4 EMC .
9.3.5 Soft errors .
9.3.6 Signal integrity summary and trends
9.4 Variability... .. . . . . . . . . . . . .
9.4.1 Spatial vs. time-based variations
9.4.2 Global vs. local variations .. ..
9.4.3 Transistor matching . . . . . . .
9.4.4 From deterministic to probabilistic design
9.4.5 Can the variability problem be solved? . . 559
9.5 Reliability . . .. . . . . . 559
9.5.1 Punch-through.. . .. . 560
9.5.2 Electromigration ... . . 560
9.5.3 Hot-carrier degradation . 563
9.5.4 Negative bias temperature instability (NBTI) . 568
9.5.5 Latch-up . 569
9.5.6 Electro-Static Discharge (ESD) . . . . . . . . . 573
9.5.7 Charge injection during th e fabrication process . 578
9.5.8 Reliability summary and trends . . 578
9.6 Design organisation. . 579
9.7 Conclusions . 581
9.8 References. . 583
9.9 Exercises . . 587
10 Testing, yield, packaging, debug and failure analysis 589
10.1 Introduction . . . . . . . 589
10.2 Testing . 591
10.2.1 Basic IC tests. . . . . . 594
10.2.2 Design for testability . . 608
10.3 Yield . . . . . . . . . . . . . . . 610
10.3.1 A simple yield model and yield control. . 614
10.3.2 Design for manufacturability . 620
10.4 Packaging . . . . . . . . . . 623
10.4.1 Introduction . 623
10.4.2 Package categories . . . . 624
10.4.3 Packaging process flow . . 627
10.4.4 Electrical aspects of packaging . 633
10.4.5 Thermal aspects of packaging . . 635
10.4.6 Reliability aspects of packaging . . 637
10.4.7 Future trends in packaging technology . 639
10.4.8 System-on-a-chip (SoC) versus system-in-a-package
(SiP) . . . . . . . . . . . . . . . . . . . . . 641
10.4.9 Quality and reliability of packaged dies . 645
10.4.10 Conclusions . . . . . . . . 647
10.5 Potential first silicon problems . 648
10.5.1 Problems with testing . . . . . . . . . . . 648
10.5.2 Problems caused by marginal or out-of-specification
processing . . . . . . . . . . . . . 650
10.5.3 Problems caused by marginal design . . . . . . . . 653
10.6 First- silicon debug and failure analysis . 654
10.6.1 Introduction . 654
10.6.2 Iddq and Ll1ddq testing . . . . . . 654
10.6.3 Traditional debug, diagnosis and failure analysis
(FA) techniques 655
10.6.4 More recent debug and failure analysis techniques 664
10.6.5 Observing the failure. . . . . . . . . . . . . . . . . 675
10.6.6 Circuit edit ing techniques 679
10.6.7 Design for Debug and Design for Failure Analysis . 682
10.7 Conclusions . 683
10.8 References. . 684
10.9 Exercises . . 686
11 Effects of scaling on MOS Ie design and consequences
for the roadmap 687
11.1 Introduction. . . . . . . . . . . 687
11.2 Transistor scaling effects . . . . 689
11.3 Interconnection scaling effects . 690
11.4 Scaling consequences for overall chip performance and robustness .
11.5 Potenti al limit ati ons of t he pace of scaling
11.6 Conclusions
11.7 References .
11.8 Exercises .