不知道可不可以这样弄：外面有二个相同频率不同源的时钟输入到fpga，然后内部通过我的逻辑选择将哪一个时钟输入给pll倍频分频，不知道这样可不可以。有下面错误提示，不知道能不能解决实现。ERRORhysDesignRules:1452 - Unsupported PLL_ADV configuration. The signal clksel on the CLKIN1 pin of PLL_ADV comp u_pll/pll_base_inst/PLL_ADV is not driven by an IOB, BUFIO2, BUFIO2_2CLK, BUFG, BUFGCTRL, or DCM and routing for this connectivity is not available.
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发表于 2014-5-27 10:05:36
hysDesignRules:1452 - Unsupported PLL_ADV configuration. The signal clksel on the CLKIN1 pin of PLL_ADV comp u_pll/pll_base_inst/PLL_ADV is not driven by an IOB, BUFIO2, BUFIO2_2CLK, BUFG, BUFGCTRL, or DCM and routing for this connectivity is not available.
发表于 2014-5-27 13:23:50
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