DC综合报的warning。。。。

ICSYS

我用 write -format verilog -hierarchy -output file.v       write_sdf  -version 2.1 /home/project/syn/sdf/file.sdf
       write_sdc  /home/project/sdc/file.sdc
命令无法产生网表和SDF SDC 文件，顺便，产生.db文件干吗用？
有高手清楚的话不吝指教哈~谢谢了哈~
主要问题如下；
warning： can't find the design PS_IBUF...
warning： can't find the design PS_OBUF...
(这两个buffer是设计代码里在输入输出端口上加的buffer)
warning： design 'design_core' has '2' unresolved references...

第二个疑问是；log里的提示。。。
linking design ‘design_core'
using the following design and libraries...
design_core             /home/project/syn/src/design_core.db

我搞不懂的是我的src下面只有.v设计文件，怎么产生了
design_core.db库文件呢？而且我设置过综合的target_library是DC目录下synopsys的库，怎么产生了上面那个design_core.db库呢？请大侠们指教啊...


==================================log===================
read_file -format verilog {/home/project/syn/src/design_core.v}
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/standard.sldb'
  Loading link library 'gtech'
Loading verilog file '/home/project/syn/src/design_core.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/project/syn/src/design_core.v==================================================
set_driving_cell -lib_cell PS_IBUF -pin Z [all_inputs]
Warning: Design 'design_core' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
Error: Cannot find the specified driving cell in memory.   (UID-993)

idbi

发log

ICSYS

发log
idbi 发表于 2014-5-17 10:27

                               
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Log里有很多warning ..主要是；Warning: design.v has '2' unresolved references.....
warning： can't find the design PS_IBUF...
warning： can't find the design PS_OBUF...
(这两个buffer是设计代码里在输入输出端口上加的buffer)
warning： design 'design_core' has '2' unresolved references...

第二个疑问是；log里的提示。。。
linking design ‘design_core'
using the following design and libraries...
design_core             /home/project/syn/src/design_core.db

我搞不懂的是我的src下面只有.v设计文件，怎么产生了
design_core.db文件呢？请大侠们指教啊...


==================================log===================
read_file -format verilog {/home/project/syn/src/design_core.v}
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/standard.sldb'
  Loading link library 'gtech'
Loading verilog file '/home/project/syn/src/design_core.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/project/syn/src/design_core.v==================================================
set_driving_cell -lib_cell PS_IBUF -pin Z [all_inputs]
Warning: Design 'design_core' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
Error: Cannot find the specified driving cell in memory.   (UID-993)

ICSYS

set_fanout_load 2.0 [all_outputs]  
Information: Building the design 'PS_IBUF'. (HDL-193)
Warning: Can't find the design 'PS_IBUF'

in the library 'WORK'. (LBR-1)


set_clock_uncertainty -setup 1.0    [get_clocks $clk_name]
Warning: Design 'design_core' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
Warning: Design 'design_core' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
1


诸如此类的。。。

ICSYS

请大侠们给看看 log 啊。谢谢啦。

ICSYS

Linking design 'design_core'
  Using the following designs and libraries:
  --------------------------------------------------------------------------
  SPI_CORE                    /home/project/syn/src/design_core.db


===============================================

ICSYS

ding again

trippa

首先将你写的两个Buffer也要读入。其次set_driving_cell 用的单元的是标准单元库你的逻辑单元而不是你自己写的。

ICSYS

首先将你写的两个Buffer也要读入。其次set_driving_cell 用的单元的是标准单元库你的逻辑单元而不是你自己写 ...
trippa 发表于 2014-5-22 09:22

                               
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谢谢兄弟，对RTL代码输入输出端口添加buffer做成pad然后综合的。是不是对每一个输入输出端口添加的buffer都要用set_driving_cell命令进行指定？

trippa

回复 9# ICSYS

为何要自己为输入输出添加BUffer？对输入端口设置set_driving_cell,输出端口set_load。