关于DC的一些warning，求帮助，谢谢！

cjy383554

Warning: Verilog writer has added 2 nets to module triangle_0 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Verilog writer has added 1 nets to module fir15_0 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Verilog writer has added 1 nets to module fir31 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Verilog writer has added 2 nets to module triangle_1 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Verilog writer has added 11 nets to module ram using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Verilog writer has added 1 nets to module fir15_1 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)

在做一个项目的时候遇见了这些警告，不知道这些警告该怎么处理？谢谢了！！

cjy383554

自己顶一个，求大侠帮助，谢谢！！

muylor

应该是module有输出的port 没接，DC自动添加了net。可以用change_names 命令将DC自动添加的net更改一下名字。不改也没事。最好在例化时将不用的输出port也写上一个信号。

liana3237

waived

cjy383554

回复 3# muylor


        我看了一下代码，发现这些warning应该是由于一些端口没有用到，空置了一些端口，所以这样警告，假设不处理的话会有什么影响呢？还有您说不用的端口加上信号，这个具体怎么加信号呢？麻烦您了！谢谢！谢谢！

muylor

回复 5# cjy383554


   不用管也没关系。
如果改，自己定义一个信号wire  xxx_nc;  接到输出悬空port上就可。