Xlinx spartan6 DDR2 ip 硬核调用编译问题

ypdzq · 发表于 2014-3-25 16:58:27

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大家好：我写了一个test工程，在工程中调用SPARTAN6的硬核，但是老是出现下面的语句：
Regenerate Core - DDR2: All required files are available.

Process "Regenerate Core" failed

没有办法正常编译，大家帮忙看看，谢谢了！

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:32:30 03/19/2014
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define time_bd 10'd54 //baudrate:57600bit/s
`define half_time_bd 10'd27 //baudrate:57600bit/s
`define cmd_read 3'b001
`define cmd_write 3'b000
module test(
//globle input signal
input clk,
input rst,
//uart interface
input rx,
output tx,
//interface between ddr2 dram and fpga
inout [15:0] mcb3_dram_dq,
output [12:0] mcb3_dram_a,
output [2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
inout mcb3_rzq,
inout mcb3_zio,
output mcb3_dram_udm,
output c3_calib_done,
//output c3_clk0,
//output c3_rst0,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n
);
//instantiation DDR2 Module
wire [15:0] mcb3_dram_dq;
wire [12:0] mcb3_dram_a;
wire [2:0] mcb3_dram_ba;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_odt;
wire mcb3_dram_cke;
wire mcb3_dram_dm;
wire mcb3_dram_udqs;
wire mcb3_dram_udqs_n;
wire mcb3_rzq;
wire mcb3_zio;
wire mcb3_dram_udm;
wire c3_sys_clk;
wire c3_sys_rst_n;
wire c3_calib_done;
wire c3_clk0;
wire c3_rst0;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
assign c3_sys_clk = clk;
assign c3_sys_rst_n = ~rst;
//ddr2_mcb user command interface
//reg c3_p0_cmd_clk;
wire c3_p0_cmd_en;
wire [2:0] c3_p0_cmd_instr;
wire [5:0] c3_p0_cmd_bl;
wire [29:0] c3_p0_cmd_byte_addr;
wire c3_p0_cmd_empty;
wire c3_p0_cmd_full;
assign c3_p0_cmd_en = (cmd_user == 2'b00)? cmd_en_wr : (cmd_user == 2'b01)? cmd_en_rd : 1'b0;
assign c3_p0_cmd_instr = (cmd_user == 2'b01)? `cmd_read : `cmd_write;
assign c3_p0_cmd_bl = 6'h3f;
assign c3_p0_cmd_byte_addr = addr_user;
//ddr2_mcb user writing interface
reg c3_p0_wr_clk;
reg c3_p0_wr_en;
reg [15:0] c3_p0_wr_mask;
reg [127:0] c3_p0_wr_data;
wire c3_p0_wr_full;
wire c3_p0_wr_empty;
wire [6:0] c3_p0_wr_count;
wire c3_p0_wr_underrun;
wire c3_p0_wr_error;
//ddr2_mcb user reading interface
reg c3_p0_rd_clk;
reg c3_p0_rd_en;
reg [127:0] c3_p0_rd_data;
wire c3_p0_rd_full;
wire c3_p0_rd_empty;
wire [6:0] c3_p0_rd_count;
wire c3_p0_rd_overflow;
wire c3_p0_rd_error;
DDR2 # (
.C3_P0_MASK_SIZE(16),
.C3_P0_DATA_PORT_SIZE(128),
.DEBUG_EN(1),
.C3_MEMCLK_PERIOD(3200),
.C3_CALIB_SOFT_IP("TRUE"),
.C3_SIMULATION("FALSE"),
.C3_RST_ACT_LOW(0),
.C3_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C3_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
.C3_NUM_DQ_PINS(16),
.C3_MEM_ADDR_WIDTH(13),
.C3_MEM_BANKADDR_WIDTH(3)
)
MY_DDR2 (
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_n (c3_sys_rst_n),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm),
.c3_clk0 (c3_clk0),
.c3_rst0 (c3_rst0),
.c3_calib_done (c3_calib_done),
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
.c3_p0_cmd_clk (c3_p0_cmd_clk),
.c3_p0_cmd_en (c3_p0_cmd_en),
.c3_p0_cmd_instr (c3_p0_cmd_instr),
.c3_p0_cmd_bl (c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty (c3_p0_cmd_empty),
.c3_p0_cmd_full (c3_p0_cmd_full),
.c3_p0_wr_clk (c3_p0_wr_clk),
.c3_p0_wr_en (c3_p0_wr_en),
.c3_p0_wr_mask (c3_p0_wr_mask),
.c3_p0_wr_data (c3_p0_wr_data),
.c3_p0_wr_full (c3_p0_wr_full),
.c3_p0_wr_empty (c3_p0_wr_empty),
.c3_p0_wr_count (c3_p0_wr_count),
.c3_p0_wr_underrun (c3_p0_wr_underrun),
.c3_p0_wr_error (c3_p0_wr_error),
.c3_p0_rd_clk (c3_p0_rd_clk),
.c3_p0_rd_en (c3_p0_rd_en),
.c3_p0_rd_data (c3_p0_rd_data),
.c3_p0_rd_full (c3_p0_rd_full),
.c3_p0_rd_empty (c3_p0_rd_empty),
.c3_p0_rd_count (c3_p0_rd_count),
.c3_p0_rd_overflow (c3_p0_rd_overflow),
.c3_p0_rd_error (c3_p0_rd_error)
);
//operation and variable defination for uart interface
reg tx_en;
reg [7:0] tx_data;
wire rx;
wire tx;
wire tx_busy;
wire rx_req;
wire [7:0] rx_data;
reg op_action;
reg [3:0] cnt_action;
reg [7:0] cnt_rx;
reg [71:0] instr_rx;
//get user command from pc
always @( posedge clk )
if(rst)
cnt_rx <= 8'd0;
else if(rx_req)
cnt_rx <= cnt_rx + 1'b1;
else
cnt_rx <= 8'd0;
always @( posedge clk )
if(rst)
instr_rx <= 72'h0;
else if(cnt_rx == `half_time_bd)
instr_rx <= {instr_rx[63:0],rx_data};
//detected active fram-ahead and get command from pc
reg order_wr;
reg [1:0] cmd_user;
reg [29:0] addr_user;
always @( posedge clk )
if(rst) begin
order_wr <= 1'b0; //write ddr2 dram from min. number to max. number
cmd_user <= 2'b0; //00: user write dram command, 01:user read dram command
addr_user <= 30'b0;
cnt_action <= 4'd0;
op_action <= 1'b0;
end
else if((instr_rx[71:64]==8'hee)&&(instr_rx[31:24]==8'hff)&&(instr_rx[23:16]==8'hfc)&&(instr_rx[15:8]==8'hff)&&(instr_rx[7:0]==8'hff)) begin
order_wr <= instr_rx[63];
cmd_user <= instr_rx[59:58];
addr_user <= {instr_rx[57:32],4'b0000};
if(cnt_action < 4'd10) begin
cnt_action <= cnt_action + 1'b1;
op_action <= 1'b1;
end
else begin
op_action <= 1'b0;
end
end
else begin
order_wr <= 1'b0; //write ddr2 dram from min. number to max. number
cmd_user <= 2'b0; //00: user write dram command, 01:user read dram command
addr_user <= 30'b0;
cnt_action <= 4'd0;
op_action <= 1'b0;
end
//send data of dram to pc according to user command
parameter read_idle = 6'd0;
parameter read_cmd1 = 6'd1;
parameter read_cmd2 = 6'd2;
parameter read_fifo1 = 6'd3;
parameter read_fifo2 = 6'd4;
parameter read_fifo3 = 6'd5;
parameter read_data00 = 6'd6;
parameter read_data01 = 6'd7;
parameter read_data10 = 6'd8;
parameter read_data11 = 6'd9;
parameter read_data20 = 6'd10;
parameter read_data21 = 6'd11;
parameter read_data30 = 6'd12;
parameter read_data31 = 6'd13;
parameter read_data40 = 6'd14;
parameter read_data41 = 6'd15;
parameter read_data50 = 6'd16;
parameter read_data51 = 6'd17;
parameter read_data60 = 6'd18;
parameter read_data61 = 6'd19;
parameter read_data70 = 6'd20;
parameter read_data71 = 6'd21;
parameter read_data80 = 6'd22;
parameter read_data81 = 6'd23;
parameter read_data90 = 6'd24;
parameter read_data91 = 6'd25;
parameter read_data100 = 6'd26;
parameter read_data101 = 6'd27;
parameter read_data110 = 6'd28;
parameter read_data111 = 6'd29;
parameter read_data120 = 6'd30;
parameter read_data121 = 6'd31;
parameter read_data130 = 6'd32;
parameter read_data131 = 6'd33;
parameter read_data140 = 6'd34;
parameter read_data141 = 6'd35;
parameter read_data150 = 6'd36;
parameter read_data151 = 6'd37;
parameter read_judge = 6'd38;
reg cmd_en_rd;
reg [5:0] state_rd;
reg [7:0] number_rd;
always @( posedge clk )
if(rst || (!c3_calib_done)) begin
cmd_en_rd <= 1'b0;
c3_p0_rd_clk <= 1'b0;
c3_p0_rd_en <= 1'b0;
state_rd <= read_idle;
number_rd <= 8'd0;
end
else if(c3_p0_cmd_instr == `cmd_read) begin
case(state_rd)
read_idle: begin
cmd_en_rd <= 1'b0;
c3_p0_rd_clk <= 1'b0;
c3_p0_rd_en <= 1'b0;
state_rd <= read_cmd1;
number_rd <= 8'd0;
end
read_cmd1: begin
if(c3_p0_cmd_empty) begin
cmd_en_rd <= 1'b1;
state_rd <= read_cmd2;
end
end
read_cmd2: begin
cmd_en_rd <= 1'b0;
state_rd <= read_fifo1;
end
read_fifo1: begin
c3_p0_rd_clk <= 1'b0;
c3_p0_rd_en <= 1'b1;
state_rd <= read_fifo2;
end
read_fifo2: begin
c3_p0_rd_clk <= 1'b1;
state_rd <= read_fifo3;
number_rd <= number_rd + 1'b1;
end
read_fifo3: begin
c3_p0_rd_clk <= 1'b0;
state_rd <= read_data00;
end
read_data00: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[7:0];
state_rd <= read_data01;
end
end
read_data01: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data10;
end
end
read_data00: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[7:0];
state_rd <= read_data01;
end
end
read_data01: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data10;
end
end
read_data10: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[15:8];
state_rd <= read_data11;
end
end
read_data11: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data20;
end
end
read_data20: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[23:16];
state_rd <= read_data21;
end
end
read_data21: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data30;
end
end
read_data30: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[31:24];
state_rd <= read_data31;
end
end
read_data31: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data40;
end
end
read_data40: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[39:32];
state_rd <= read_data41;
end
end
read_data41: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data50;
end
end
read_data50: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[47:40];
state_rd <= read_data51;
end
end
read_data51: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data60;
end
end
read_data60: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[55:48];
state_rd <= read_data61;
end
end
read_data61: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data70;
end
end
read_data70: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[63:56];
state_rd <= read_data71;
end
end
read_data71: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data80;
end
end
read_data80: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[71:64];
state_rd <= read_data81;
end
end
read_data81: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data90;
end
end
read_data90: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[79:72];
state_rd <= read_data91;
end
end
read_data91: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data100;
end
end
read_data100: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[87:80];
state_rd <= read_data101;
end
end
read_data101: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data110;
end
end
read_data110: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[95:88];
state_rd <= read_data111;
end
end
read_data111: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data120;
end
end
read_data120: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[103:96];
state_rd <= read_data111;
end
end
read_data121: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data130;
end
end
read_data130: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[111:104];
state_rd <= read_data131;
end
end
read_data131: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data140;
end
end
read_data140: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[119:112];
state_rd <= read_data141;
end
end
read_data141: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_data150;
end
end
read_data150: begin
if(!tx_busy) begin
tx_en <= 1'b1;
tx_data <= c3_p0_rd_data[127:120];
state_rd <= read_data151;
end
end
read_data151: begin
if(!tx_busy) begin
tx_en <= 1'b0;
state_rd <= read_judge;
end
end
read_judge: begin
if(number_rd == 8'd64)
state_rd <= read_idle;
else
state_rd <= read_fifo1;
end
default: begin
cmd_en_rd <= 1'b0;
c3_p0_rd_clk <= 1'b0;
c3_p0_rd_en <= 1'b0;
state_rd <= read_cmd1;
number_rd <= 8'd0;
end
endcase
end
//write data to dram according to user command
reg cmd_en_wr;
reg [3:0] state_wr;
reg [7:0] number_wr;
parameter write_idle = 4'd0;
parameter write_data1 = 4'd1;
parameter write_data2 = 4'd2;
parameter write_data3 = 4'd3;
parameter write_judge = 4'd4;
parameter write_cmd1 = 4'd5;
parameter write_cmd2 = 4'd6;
always @(posedge clk)
if(rst || (!c3_calib_done)) begin
cmd_en_wr <= 1'b0;
c3_p0_wr_clk <= 1'b0;
c3_p0_wr_en <= 1'b0;
c3_p0_wr_mask <= 16'd0;
c3_p0_wr_data <= 128'd0;
state_wr <= write_idle;
number_wr <= 8'd0;
end
else if(c3_p0_cmd_instr == `cmd_write) begin
case(state_wr)
write_idle: begin
cmd_en_wr <= 1'b0;
c3_p0_wr_clk <= 1'b0;
c3_p0_wr_en <= 1'b0;
c3_p0_wr_mask <= 16'd0;
c3_p0_wr_data <= 128'd0;
state_wr <= write_data1;
number_wr <= 8'd0;
end
write_data1: begin
if(c3_p0_wr_empty) begin
state_wr <= write_data2;
end
end
write_data2: begin
c3_p0_wr_en <= 1'b0;
c3_p0_wr_clk <= 1'b0;
c3_p0_wr_data <= {number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr,number_wr};
c3_p0_wr_mask <= 16'd0;
state_wr <= write_data3;
end
write_data3: begin
c3_p0_wr_clk <= 1'b1;
state_wr <= write_judge;
number_wr <= number_wr + 1'b1;
end
write_judge: begin
c3_p0_wr_clk <= 1'b0;
if((number_wr == 8'd64)&&c3_p0_wr_full) begin
state_wr <= write_cmd1;
number_wr <= 8'd0;
end
else begin
state_wr <= write_data2;
end
end
write_cmd1: begin
if(c3_p0_cmd_empty) begin
cmd_en_wr <= 1'b1;
state_wr <= write_cmd2;
end
end
write_cmd2: begin
cmd_en_wr <= 1'b0;
state_wr <= write_idle;
end
default: begin
cmd_en_wr <= 1'b0;
c3_p0_wr_clk <= 1'b0;
c3_p0_wr_en <= 1'b0;
c3_p0_wr_mask <= 16'd0;
c3_p0_wr_data <= 128'd0;
state_wr <= write_data1;
number_wr <= 8'd0;
end
endcase
end
uart #
(
.time_spec (`time_bd), //baudrate = 57600, 50_000_000/57600/16 = 54
.half_time_spec (`half_time_bd) //time_spec/2 = 10'd27
)
my_uart(
.clk (clk),
.rst (rst),
.tx_en (tx_en),
.rx (rx),
.tx_data (tx_data),
.tx_busy (tx_busy),
.tx (tx),
.rx_data (rx_data),
.rx_req (rx_req)
);
endmodule

复制代码

shiyinjita · 发表于 2014-3-27 19:01:57

回复 1# ypdzq

把DDR2的IP核删掉就可以了，用文件代替

ypdzq · 发表于 2014-3-28 09:11:45

回复 2# shiyinjita

我试过了，如果直接用rtl文件夹下面的*.v文件，编译时可以通过的，但是没有办法综合。综合的时候报一堆莫名其妙的错误，所以只能用硬核了。

ypdzq · 发表于 2014-3-28 09:15:10

回复 1# ypdzq
关于这个问题，原因貌似找到了我用的是ISE13.1版本的，我把版本换成ISE14.6就可以正常编译和综合了，所以可能是ISE13.1固有的问题。

ypdzq · 发表于 2014-3-28 09:22:45

换成ISE14.6后，问题是解决了，但是新的问题出现了：
用的CLK是50MHz的，CLK主要用在两个地方：1、送给MCB硬核控制模块，模块内部的PLL用了IO BUF；2、用在MCB控制部分，做posedge clk用。
问题来了，translate和map时报错，意思好像是同一个clk不能既用在IO BUF又用在posedge clk，后面没有办法，就只能用MCB PLL输出的一路C3_CLK0做系统时钟。
关于这一方面，大家有谁比较了解，给讲讲，谢谢了！

shiyinjita · 发表于 2014-3-28 21:28:35

回复 3# ypdzq

我用13.3 是用的。v文件完全没有问题的

574920045 · 发表于 2014-4-3 08:53:29

回复 5# ypdzq

你接串口是想用串口读写ddr吗？？？？

ypdzq · 发表于 2014-4-3 15:38:37

回复 7# 574920045

你好，我接了串口，是打算用串口来调试。首先发送一个命令串：EE 00 00 00 00 FF FC FF FF
EE：是帧头
FF FC FF FF：是帧尾
000000：是操作命令，000000代表写命令，000001代表读命令，写或者读操作为对1k words地址连续操作，即一次命令为连续的1k words地址的操作。
00000000000000000000000000：代表操作对应的地址。
注：中间4个bytes为命令，前6bits为指令，后26bits为操作地址

我用的1port 128bit的口，即读写操作，一次性可以读出或者写入16个bytes的数据

写操作时：（指令：EE 00 00 00 00 FF FC FF FF，PC通过串口发送给FPGA）
step1:先把wr_fifo写满，BL=64，所以一次性写入64*128bits = 1024 bytes, 512 words，也就是将要向DDR2的0-512地址空间写数据；
向wr_fifo中写的数据为(共64组，1024个bytes的数据)：
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
.......
3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f 3f

step2:cmd接口发送wr指令，完成MCB对DDR2的写操作；

读操作时：（指令：EE 04 00 00 00 FF FC FF FF，PC通过串口发送给FPGA）
step1: cmd接口发送rd指令，完成MCB对DDR2对应地址的读操作；
step2: 从rd_fifo把数据读出来，并通过串口把1024 bytes发送给PC

574920045 · 发表于 2014-4-3 15:48:55

回复 8# ypdzq

我先在也在调xilinx的MCB，以后多指教啊！不指导你调好了吗？是在xilinx的官方开发板子上调的吗？想问问你的串口可接处理器？难道你内部写了操作逻辑？你是在example的例子上调试的吗？多多指教啊！！！我现在不确定接mcb操作读写用什么方法！

ypdzq · 发表于 2014-4-3 15:49:35

现在代码已经综合并生成了下载文件，下到板子里面后，发送ee 00 00 00 00 ff fc ff ff
没有任何反应，想用modelsim仿真，代码中操作要等那个c3_calib_done信号拉高后才能进行，但是我仿真时间已经跑到52ms了，c3_calib_done还是没有拉高，没有办法看仿真波形。
怎么办，大家有没有好的调试方法，分享一下，谢谢了！
我用的是SPARTRAN6 XC6SLX16

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