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发表于 2014-2-25 10:39:43
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回复 4# loveyahoo
好像看到一篇guide也是这么说的,我再去看看,谢谢你了。说到verilogA,我也正想编一个理想的动态锁存比较器,代码如下,希望比较器功能:时钟为高时进行复位,输出(差分)都被拉高,时钟为低时,比较器只进行一次比较。不过还没改成,能麻烦你帮我看一下吗?
`include "discipline.h"
`include "constants.h"
// model comp - Comparator
// enable signal is active: High
//
module COMP1_ideal_me (vin_p, vin_n, clk, vout_p, vout_n) ;
input vin_p, vin_n, clk;
output vout_p, vout_n;
electrical vin_p, vin_n, clk, vout_p, vout_n;
parameter real td = 1p from (0:inf);
//parameter real hys = 1u from (0:inf);
parameter real p_off = 0u;
parameter real n_off = 0u;
parameter real trise = 20.0p from (0:inf);
parameter real tfall = 20.0p from (0:inf);
parameter real one = 3.3;
parameter real zero = 0.0;
parameter real vth = 1.5;
parameter real slack = 10.0p from (0:inf); //slack不懂
//parameter integer init = 1; //不懂作用
//parameter integer traceflag = 1; //不懂作用
// // real vin, halfhys, outstate;
real vin, outstate1,outstate2;
analog begin
@(initial_step("ac","dc","tran","xf")) begin
vin =V(vin_p) + p_off - V(vin_n) + n_off;
outstate1 = (abs(vin) > 0.0) ? zero : one ;
outstate2 = (abs(vin) > 0.0) ? one : zero ;
//if (traceflag) begin
//$strobe("%M at Init. vout: %g hys/2:%g", V(vout), halfhys);
end
end
//vin =V(vin_p) + p_off - V(vin_n) + n_off; //不屏蔽时报错
@(cross(vin, +1, slack )) begin //报错
if (V(enable) > vth) begin
outstate1 = one;
outstate2 = zero;
//if(traceflag)
//$strobe("%M at %g sec. output going high vin(p-n): %g hys/2:%g",
//$abstime, vin, halfhys); //这些话不知道干什么用的,所以屏蔽了
end
end
@(cross(vin, -1, slack)) begin
if (V(enable) > vth) begin
outstate1 = zero;
outstate2 = one;
//if(traceflag)
//$strobe("%M at %g sec. output going low vin(p-n): %g hys/2:%g",
// $abstime, vin, halfhys);
end
end
V(vout_p) <+ transition (outstate1, td, trise, tfall );
V(vout_n) <+ transition (outstate2, td, trise, tfall );
end
endmodule |
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