xilinx pcie ip仿真 trn_link_up一直不通

by991 · 发表于 2013-12-19 11:49:34

回复 3# shiyinjita
trn_lnk_up一直不拉低基本上就是参数定义中没有设仿真的缘故

by991 · 发表于 2013-12-19 13:54:20

回复 8# shiyinjita

另外，请教一个问题，怎么使用xilinx生成的example程序仿真CPLD TLP啊？直接使用仿真文件里面的TSK_TX_COMPLETION_DATA的task来发送，设备端好像接收不到CPLD TLP。

shiyinjita · 发表于 2013-12-20 12:03:44

回复 11# by991

在V系列的芯片中，好像需要定义simulation这个函数

如果想发完成包，那么相当于DMA形式，你必须先定义cfg[4]中的寄存器

by991 · 发表于 2013-12-20 13:23:28

回复 13# shiyinjita

谢谢！cfg[4]在哪个文件里面？能告诉详细流程吗？定义好cfg[4]中的寄存器，发送TSK_TX_COMPLETION_DATA这个task就可以收到cpld tlp了？再次感谢回复，困扰了很久的问题……

by991 · 发表于 2013-12-20 13:26:36

回复 13# shiyinjita

您好！cfg[4]寄存器在哪个文件里面？设置好这个寄存器然后发送TSK_TX_COMPLETION_DATA就可以收到cpld的tlp了？能提供一个详细的接收cpld tlp的流程吗？很感谢！

shiyinjita · 发表于 2013-12-20 19:56:23

回复 15# by991

是配置寄存器，地址为04 具体忘记那个了，你看看，

neufeifatonju · 发表于 2014-2-26 21:05:28

你用isim仿真的时候，能出波形吗，你系统是64位的吗。我仿真出现如下提示：
ISim O.87xd (signature 0x2f00eba5)
This is a Full version of ISim.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/xilinx_pcie_2_1_ep_7x.v" Line 203.  For instance EP/\ext_clk.pipe_clock_i /, width 1 of formal port CLK_RXUSRCLK is not equal to width 8 of actual signal PIPE_RXUSRCLK_IN.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/xilinx_pcie_2_1_ep_7x.v" Line 204.  For instance EP/\ext_clk.pipe_clock_i /, width 8 of formal port CLK_RXOUTCLK_OUT is not equal to width 1 of actual signal PIPE_RXOUTCLK_IN.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_top.v" Line 752.  For instance pcie_top_i/axi_basic_top/, width 7 of formal port trn_rbar_hit is not equal to width 8 of actual signal trn_rbar_hit.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 353.  For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNTD is not equal to width 64 of actual signal trn_td.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 354.  For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNTREM is not equal to width 1 of actual signal trn_trem.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 547.  For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNRD is not equal to width 64 of actual signal trn_rd.
WARNING: File "E:/ISE/kc705_pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 548.  For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNRREM is not equal to width 1 of actual signal trn_rrem.
ERROR

ortability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict.  Current memory usage is 2093456 kb.  You can
try increasing your system's physical or virtual memory.  If you are using a
Win32 system, you can increase your application memory from 2GB to 3GB using
the /3G switch in your boot.ini file. For more information on this, please
refer to Xilinx Answer Record #14932. For technical support on this issue,
you can open a WebCase with this project attached at
http://www.xilinx.com/support.
ERROR: The simulation failed to launch for the following reason:
The Simulation shut down unexpectedly during initialization.  Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation.  If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.

The simulation has terminated.
还望指教，多谢

neufeifatonju · 发表于 2014-2-27 10:16:16

ERRORortability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict. Current memory usage is 2093456 kb. 仿真有这么占资源吗

neufeifatonju · 发表于 2014-2-27 12:21:42

用modelsim出来结果了，isim一直提示超出内存，这东西这么占内存啊，别人用isim仿真都是用的64位系统吗，感谢楼上的讨论

ncchengang · 发表于 2014-5-27 21:59:24

原来这样哦

[求助] xilinx pcie ip仿真 trn_link_up一直不通

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