phd thesis (high speed SAR ADC in detail)

dudiaoke

phd thesis (high speed SAR ADC in detail)

criffs

high speed SAR ADC in detail, 多快速度

colindeng

需要，学习了。

fhchen2002

回复 1# dudiaoke


Author: Masoud Ensafdaran
Ph.D. thesis in year 2013
University of Texas, Dallas

Contents

• Introduction
• ADC Basics
• 250MS/s Successive ADC
• Switched Current Integrating Sampler
• ADC Based Phase to Digital Converter
• Conclusion
• References

Vita (of Mosoud Ensafdaran)

Masoud Ensafdaran was born in Shiraz, Iran. After graduating from Rajaei High School in 2001, Masoud entered Shiraz University, Shiraz, Iran. He received a Bachelor of Science in Electrical Engineering from Shiraz University in February 2006. He started his study as a Master student at Sharif University of Technology, Tehran, Iran in September 2006 and earned his Master’s degree in microelectronics in January 2009. In August 2009, he entered the doctoral program in Electrical Engineering at The University of Texas at Dallas.

wfcawy

the second half of the thesis talks about PDC in DPLLs, a little away from its title

fixit

kankan

jimway

kankan

andy2000a

HIGH SPEED SUCCESSIVE APPROXIMATION ADC AND ITS APPLICATIONS
by
Masoud Ensafdaran

Data converters are required in many applications such as serial link, wireless communication
and clock generation circuits. For example, analog to digital converters (ADCs) are usually
time-interleaved to implement very high speed ADCs in serial link and ultra wide-band
(UWB) receivers. Phase to digital conversion is also a critical building block of digital
phase locked loops (DPLLs). With recent advancements in speed and power consumption,
successive approximation ADCs (SAR ADCs) have achieved significant attention. The focus
of this dissertation is on the design of a high speed and low power SAR ADC. The main
target application of our ADC is time-interleaved ADCs and DPLLs.
Several new techniques are proposed to realize a single-stage 10b 250MS/s SAR ADC. A
double capacitor-array digital to analog converter (DAC) with top plate sampling enables
the use of simple switch circuitry with faster settling time while improving power efficiency.
The ADC also employs a two-speed variable clock generator to exploit the reduced DAC
settling time requirements. A semi-dynamic comparator modified for low voltage design is
used to achieve fast decision and reset times. A multiple latch based SAR logic decreases
vi
後面才說 250M SAR

所以 SAR 可做到 250m ??

那目前 PIPELINE AD 可到多快 ???

podcast

thx for sharing~

huqr1226

多谢楼主分享……