Verilog and SystemVerilog Gotchas:101 Common Coding Error and How to Avoid Them

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Verilog and SystemVerilog Gotchas:
          101 Common Coding Error and How to Avoid Them
by Stuart Sutherland and Don Mills
         Hardcover, 218 pages, $99 US retail price
         Copyright 2006, Springer (formerly Kluwer), Norwell MA
         ISBN: 978-0-387-71714-2



This book has a mistake on almost every page!  On purpose.  The book shows common coding mistakes that the authors or others have made in their Verilog or SystemVerilog code.  Often these mistakes looked like perfectly reasonable code, but cause functional errors in simulation or synthesis that were difficult to debug.  And that's the definition of a Gotcha -- code that looks correct, but which behaves differently than expected.

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.




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ak_fisher

错误写法还是留着以后看

kevinse

多谢楼主分享

lujunfeng111

这本书的立意颇有意思。

xiachuanily

下载下来看看，起码知道常见的错误是好事

kylkzy

多谢楼主分享

skyline72

多谢楼主分享

immonster

这个号

mailtoanoopbabu

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xxiaofeng

这本书写的有些意思，反其道而行