| 
×
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册  Job title: Physical Design Engineer Department: COT-PD Location: Nanjing   Responsibilities: As member of Marvell central physical design team, you will play a challenging role in assisting multiple Marvell design groups in sign-off check includes power/signal integrity analysis (IR drop, EM, ESD), physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout, as well as maintaining power analysis and physical verification flow, custom layout and add-on tools.   Requirements: o2+ years of direct experience on IC design. BS/MS preferred.
 oKnowledge in some of the following technical areas: custom layout, PCB layout, power consumption calculate, timing, chip package.
 oProven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.
 oUnderstanding of power planning, be able to analyze the weakness of power grid and provide solution.
 oBe Familiar with Laker, Cadence Virtuoso, or Mentor DesignRev. Strong knowledge to debug Mentor’s Calibre or Synopsys’ Hercules tools.
 oBe familiar with Apache, Encounter Power System, or PrimeRail.
 oMust be programming-minded, capable of writing Tcl or Perl.
 oSelf-motivated team worker, good verbal and written communication skills.
 oKnowledge of Cadence or Synopsys Place and Route tools a big plus.
 oMust able to work under tapeout pressure and tight schedule
   更多Marvell招聘职位: http://companyadc.51job.com/companyads/2012vip/sh/marvell0120_7399/jobs.htm If you are interested in exploring a job opportunity with Marvell  please send me a copy of your resume to:  AL-China-HR@marvell.comEmail Subject: 姓名_学历_学校_工作年限_应聘岗位_意向城市; 比如: 张三_硕士_东南大学_3yrs_Platform_南京
 
 更多关注: Marvell官方微博:http://e.weibo.com/marvellcn Marvellhr官方微博:   http://weibo.com/marvellhr     |