『三味书屋』元旦送礼之五：The Kluwer 2002～2004(模拟部分)(O～W)

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	Oversampled Delta-Sigma ModulatorsAnalysis Applications and Novel Topologies Kozak, Mücahit, Kale, Izzet 2003, 230 p., Hardcover ISBN: 978-1-4020-7420-2 This item usually ships in 3-4 weeks.
	$169.00

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The analysis of the quantization noise in delta-sigma modulators is not a trivial task. State-of-the-art analysis methods include modelling the quantization noise as a uniform distributed white noise. However, it is not uncommon to observe limit cycle oscillations and tones at the output of a delta-sigma modulator. In most of the applications, these limit cycles and tones are strictly objectionable. Such an application, for instance, is a Fractional-N PLL frequency synthesizer, where idle tones and limit cycles generated from the delta-sigma modulator directly appear in the synthesized RF waveform as spurious components. The relatively small conversion bandwidth is another important limitation of delta-sigma modulators. Due to their oversampling nature, delta-sigma modulators have been used in low frequency applications.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies is full of design and analysis techniques. The book contains sufficient detail that enables readers with little background in the subject to easily follow the material in it.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies will be of interest to graduate students, researchers, and practising circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design.

[ 本帖最后由 benemale 于 2008-1-8 00:04 编辑 ]

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	Phase-Locked Loops for Wireless Communications Digital and Analog Implementations Stephens, Donald R. 1998, 400 p., Hardcover ISBN: 978-0-7923-8204-1 Order now, and we will ship when available. (Your credit card will not be charged until we ship).
	$195.00

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This is a contemporary reference work on phase-locked loops for wireless communications engineers. The coverage is comprehensive and includes summary chapters on the circuit theory needed to explain the theory and operation of phase-locked loops and the supporting mathematics necessary for analysis. These include concise discussions of Laplace transformations, z-Transformations, root locus, Bode analysis, partial fraction expansion, and others.
The material develops systematically from analog through digital loops. Included is broad coverage of synchronization methods and techniques, modern digital interpolation techniques in modem design, modem acquisition and tracking, fading channel performances, as well as practical rules-of-thumb for modem designers to use in specifying loop bandwidths for good performances. The book provides numerous real world applications, and each chapter has problem sets that reinforce important concepts presented.
Phase-Locked Loops for Wireless Communications: Digital and Analog Implementations features a complete collection of topics needed by both the wireless and traditional phase-locked loop specialist to design and analyze high performance circuits and software algorithms.

[ 本帖最后由 benemale 于 2008-1-9 22:38 编辑 ]

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	Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems Zaccaria, V., Sami, M.G., Sciuto, D., Silvano, C. 2003, 201 p., Hardcover ISBN: 978-1-4020-7377-9 This item usually ships in 3-4 weeks.
	$159.00

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The main contribution of Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems consists of the introduction of innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance Very Long Instruction Word (VLIW) microprocessors. A VLIW processor is a (generally) pipelined processor that can execute, in each clock cycle, a set of explicitly parallel operations; this set of operations is statically scheduled to form a Very Long Instruction Word.
The proposed estimation techniques are integrated into a set of tools operating at the instruction level and they are characterized by efficiency and accuracy. The aim is the definition of an overall power estimation framework, from a system-level perspective, where novel power optimization techniques can be evaluated.
The proposed power optimization techniques are addressed to the micro-architectural as well as the system level. Two main optimization techniques have been proposed: the definition of register file write inhibition schemes that exploit the forwarding paths, and the definition of a design exploration framework for an efficient fine-tuning of the configurable modules of an embedded system.

[ 本帖最后由 benemale 于 2008-1-9 22:39 编辑 ]

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	Power-Constrained Testing of VLSI Circuits Series: Frontiers in Electronic Testing , Vol. 22B Nicolici, Nicola, Al-Hashimi, Bashir M. 2003, 180 p., Hardcover ISBN: 978-1-4020-7235-2 Ships in 3 - 5 business days
	$159.00

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Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.
Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Written for:
IT specialists

[ 本帖最后由 benemale 于 2008-1-9 22:39 编辑 ]

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	Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design Mo, Fan, Brayton, Robert K. 2004, XI, 242 p., Hardcover ISBN: 978-1-4020-8040-1 This item usually ships in 2-3 business days
	$129.00

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Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability.
In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.
Written for:
CAD developers, IC designers, engineers and developers in the area of IC fabrication and IC reliability

[ 本帖最后由 benemale 于 2008-1-9 22:41 编辑 ]

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	Semiconductor Optical Amplifiers Connelly, Michael J. 2002, 184 p., Hardcover ISBN: 978-0-7923-7657-6 Ships in 3 - 5 business days
	$189.00

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The semiconductor optical amplifier (SOA) has emerged as an important component in many optical fiber communication, switching and signal processing systems. Besides its basic use as an in-line amplifier, SOAs have found use in a myriad of applications. Semiconductor Optical Amplifiers provides a comprehensive and detailed treatment of the design and applications of SOAs.
Key areas covered include:

• Historical background.
• SOA principles - theory of amplification, gain, noise, noise figure, polarisation dependence, spectral bandwidth, dynamics.
• SOA structures - travelling-wave, Fabry-Perot, DBR, DFB, multi-section, twin-guide, polarisation insensitive configurations, low-reflectivity coatings, angled facets, high-power devices, gain clamped devices, SOA packaging.
• Bulk and quantum-well semiconductor materials.
• Static and dynamic modelling - travelling-wave equations, recombination mechanisms, analytical approximations and computer modelling techniques.
• SOA optimisation, slow and fast pulse amplification.
• Applications in optical communication systems - direct detection and coherent receivers, amplified light detection statistics, preamplifier, in-line amplifier, booster amplifier, amplifier chains, SOA based optical network topologies, TDM, WDM, soliton transmission, system experiments, analog systems.
• Non-linear behaviour - cross-gain modulation, self-phase and cross-phase modulation, four-wave mixing, frequency chirping, bistability.
• Functional applications - intensity modulator, phase modulator, switch, add/drop multiplexer, wavelength converter, in-line detector, dispersion compensator, pulse-shaper, all-optical clock recovery, loop mirror configurations, logic functions.
• SOA photonic integrated circuits.
• Current developments and future prospects.

Semiconductor Optical Amplifiers is an invaluable information source for researchers and engineers involved in SOA and optical systems design and manufacturing. It is also useful to graduate students, in optoelectronics, optical communications and optical engineering, entering this rapidly growing and exciting field of research and development.
Written for:
Researchers and engineers involved in SOA and optical systems design and manufacturing, graduate students in optoelectronics, optical communications, optical engineering

[ 本帖最后由 benemale 于 2008-1-9 22:43 编辑 ]

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	Structured Electronic Design Negative-Feedback Amplifiers Verhoeven, C.J.M., van Staveren, A., Monna, G.L.E., Kouwenhoven, M.H.L., Yildiz, E. 2003, 380 p., Hardcover ISBN: 978-1-4020-7590-2 Ships in 3 - 5 business days
	$149.00

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Analog design is one of the more difficult aspects of electrical engineering. The main reason is the apparently vague decisions an experienced designer makes in optimizing his circuit. To enable fresh designers, like students electrical engineering, to become acquainted with analog circuit design, structuring the analog design process is of utmost importance.
Structured Electronic Design: Negative-Feedback Amplifiers presents a design methodology for negative-feedback amplifiers. The design methodology enables to synthesize a topology and to, at the same time, optimize the performance of that topology.
Key issues in the design methodology are orthogonalization, hierarchy and simple models. Orthogonalization enables the separate optimization of the three fundamental quality aspects: noise, distortion and bandwidth. Hierarchy ensures that the right decisions are made at the correct level of abstraction. The use of simple models, results in simple calculations yielding maximum-performance indicators that can be used to reject wrong circuits relatively fast.
The presented design methodology divides the design of negative-feedback amplifiers in six independent steps. In the first two steps, the feedback network is designed. During those design steps, the active part is assumed to be a nullor, i.e. the performance with respect to noise, distortion and bandwidth is still ideal.
In the subsequent four steps, an implementation for the active part is synthesized. During those four steps the topology of the active part is synthesized such that optimum performance is obtained. Firstly, the input stage is designed with respect to noise performance. Secondly, the output stage is designed with respect to clipping distortion. Thirdly, the bandwidth performance is designed, which may require the addition of an additional amplifying stage. Finally, the biasing circuitry for biasing the amplifying stages is designed.
By dividing the design in independent design steps, the total global optimization is reduced to several local optimizations. By the specific sequence of the design steps, it is assured that the local optimizations yield a circuit that is close to the global optimum. On top of that, because of the separate dedicated optimizations, the resource use, like power, is tracked clearly.
Structured Electronic Design: Negative-Feedback Amplifiers presents in two chapters the background and an overview of the design methodology. Whereafter, in six chapters the separate design steps are treated with great detail. Each chapter comprises several exercises. An additional chapter is dedicated to how to design current sources and voltage source, which are required for the biasing. The final chapter in the book is dedicated to a thoroughly described design example, showing clearly the benefits of the design methodology.
In short, this book is valuable for M.Sc.-curriculum Electrical Engineering students, and of course, for researchers and designers who want to structure their knowledge about analog design further.
Written for:
M.Sc.-curriculum electrical engineering students, researchers, designers

[ 本帖最后由 benemale 于 2008-1-9 22:48 编辑 ]

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	Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chipsde la Rosa, José M.; Pérez-Verdú, Belén; Rodríguez-Vázquez, Angel (Eds.) 2002, 488 p., Hardcover ISBN: 978-0-7923-7678-1 This item usually ships in 2-3 business days
	$229.00

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Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips discusses architectures, circuits and procedures for the optimum design of bandpass sigma-delta (SD) A/D interfaces for mixed-signal chips in standard CMOS technologies. The book differs from others in the very detailed and in-depth coverage of switched-current (SI) errors, which supports the design of high performance SI chips. The book starts with a tutorial presentation of the fundamentals of bandpass SD converters, their applications in communications and their most common architectures. It then presents the basic SI building blocks required for their implementation and analyzes in great detail the operation of these blocks. The influence of SI errors on the performance of the SD modulators (SDMs) is also studied. The outcome is a unique set of models which can be employed with a double purpose: namely, to support iterative procedures employed in mapping specifications onto design parameters; and to allow for accurate behavioural time-domain simulation using MATLAB-like tools. The book is completed with two case studies corresponding to modulators for AM digital radio receivers.
The analyses, models and procedures in the book support the design of SI front-ends with performance indexes comparable to those of switched-capacitor circuits, which makes a significant difference as compared to previous works in the area of SI circuits. Together with a detailed revision of the SI literature, the book presents practical recipes on how to get the maximum performance from SI circuits, and illustrates them by means of two case study chips in CMOS submicron technologies. These prototypes constitute the first reported IC realizations of SI bandpass SDMs.
Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips contains highly valuable and unique information to be used as a reference by designers of the analog front-end of mixed-signal chips. The models presented in the book will help these designers to increase their productivity. The tutorial, comprehensive coverage of all issues associated with bandpass sigma-delta converters makes the book very well suited for graduate courses. Finally, the very detailed coverage of errors and trade-offs in the operation of switched-current circuits will be found invaluable by teachers of undergraduate analog design courses.
Written for:
Designers of the analog front-end of mixed-signal chips, teachers of undergraduate analog design courses

[ 本帖最后由 benemale 于 2008-1-9 22:53 编辑 ]

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	The Design and Implementation of Low-Power CMOS Radio Receivers Shaeffer, Derek, Lee, Thomas H. 1999, 224 p., Hardcover ISBN: 978-0-7923-8518-9 Ships in 3 - 5 business days
	$163.00

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The primary goal of The Design and Implementation of Low-Power CMOS Radio Receivers is to explore techniques for implementing wireless receivers in an inexpensive complementary metal-oxide-semiconductor (CMOS) technology. Although the techniques developed apply somewhat generally across many classes of receivers, the specific focus of this work is on the Global Positioning System (GPS). Because GPS provides a convenient vehicle for examining CMOS receivers, a brief overview of the GPS system and its implications for consumer electronics is presented.
The GPS system comprises 24 satellites in low earth orbit that continuously broadcast their position and local time. Through satellite range measurements, a receiver can determine its absolute position and time to within about 100m anywhere on Earth, as long as four satellites are within view. The deployment of this satellite network was completed in 1994 and, as a result, consumer markets for GPS navigation capabilities are beginning to blossom. Examples include automotive or maritime navigation, intelligent hand-off algorithms in cellular telephony, and cellular emergency services, to name a few.
Of particular interest in the context of this book are embedded GPS applications where a GPS receiver is just one component of a larger system. Widespread proliferation of embedded GPS capability will require receivers that are compact, cheap and low-power.
The Design and Implementation of Low-Power CMOS Radio Receivers will be of interest to professional radio engineers, circuit designers, professors and students engaged in integrated radio research and other researchers who work in the radio field.

[ 本帖最后由 benemale 于 2008-1-9 23:07 编辑 ]

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	The Design of Low Noise Oscillators Hajimiri, Ali, Lee, Thomas H. 1999, 224 p., Hardcover ISBN: 978-0-7923-8455-7 Ships in 3 - 5 business days
	$142.00

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The tremendous growth in wireless and mobile communications has placed stringent requirements on channel spacing and, by implication, on the phase noise of oscillators. Compounding the challenge has been a recent drive toward implementations of transceivers in CMOS, whose inferior l/f noise performance has usually been thought to disqualify it from use in all but the lowest-performance oscillators.
Low noise oscillators are also highly desired in the digital world. The continued drive toward higher clock frequencies translates into a demand for ever-decreasing jitter.
There is a need for a deep understanding of the fundamental mechanisms governing the process by which device, substrate, and supply noise turn into jitter and phase noise. Existing models generally offer only qualitative insights, however, and it has not always been clear why they are not quantitatively correct.
The Design of Low Noise Oscillators offers a new time-variant phase noise model. By discarding the implicit assumption of time- invariance underlying many other approaches, this model is capable of making quantitative predictions of the phase noise and jitter of different types of oscillators. It is able to attribute a definite amount of phase noise to every noise source in the circuit. Because of its time-variant nature, the model also takes into account the effect of cyclostationary noise sources in a natural way. It details the precise mechanism by which low frequency noise, such as l/f noise, upconverts into close-in phase noise. An important new understanding is that rise and fall time symmetry controls such upconversion. More important, it suggests practical methods for suppressing this upconversion, so that good oscillators can be built in technologies with notoriously poor l/f noise performance (such as CMOS or GaAs MESFET).
The Design of Low Noise Oscillators will be of interest to both analog and digital circuit as well as RF circuit designers.

[ 本帖最后由 benemale 于 2008-1-9 23:07 编辑 ]