VHDL 74193建模不能综合（ISE 13.3)

jefby · 发表于 2012-10-10 21:27:52

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代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_74193 is
port(
A:in std_logic_vector(3 downto 0);
LDN,UP,DN,CLR:in std_logic;
BON,CON:out std_logic;
Q:out std_logic_vector(3 downto 0)
);
end module_74193;
architecture Behavioral of module_74193 is
signal Qt:std_logic_vector(3 downto 0);
begin
process(UP,DN,CLR,LDN)
begin
if(CLR = '1')then
Qt<= (others =>'0');
elsif(LDN = '0')then
Qt <= A;
elsif(UP'event and UP ='1')then
if(Qt = "1111")then
CON <= '1';
end if;
Qt <= Qt + 1;
elsif(DN'event and DN = '1') then
if(Qt = "0000")then
BON <= '1';
end if;
Qt <= Qt - 1;
end if;
end process;
Q <= Qt;
end Behavioral;

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综合报错：
Xst:827 - "D:/Project/Xilinx Project/My_Own/cpu_for_exercise/cpu_cisc/module_74193.vhd" line 46: Signal Qt cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
求助高手指点！！

falloutmx · 发表于 2012-10-11 10:11:36

一个process里用两个clk_event？补习下VHDL吧。写代码的时候多想想对应的硬件结构

jefby · 发表于 2012-10-13 11:46:51

回复 2# falloutmx
已经修改为两个进程，但是如何确定什么时候选用正确的计数值怎么设计啊？

process(up,clr,ldn,Qt,A)
begin
if(clr = '1')then
Qu <= (others => '0');
elsif(ldn = '0')then
Qu <= A;
elsif(up'event and up = '1')then
if(Qt = "1111")then
con <= '1';
end if;
Qu <= Qt + 1;
end if;
end process;
process(dn,clr,ldn,Qt,A)
begin
if(clr = '1')then
Qd <= (others =>'0');
elsif(ldn = '0')then
Qd <= A;
elsif(dn'event and dn = '1')then
if(Qt = "0000")then
bon <= '0';
end if;
Qd <= Qt - 1;
end if;
end process;

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求指点

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[求助] VHDL 74193建模不能综合（ISE 13.3)

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