在一个setup path中
Startpoint: jtag_INSTRUCTION_prog_spi_r_reg
(falling edge-triggered flip-flop clocked by tck)
Endpoint: jtag_REGISTER_bypass_r_reg
(rising edge-triggered flip-flop clocked by tck)
Path Group: tck
Path Type: max
------------------------------------------------------------------------------
clock tck (fall edge) 20.00 20.00
clock network delay (propagated) 0.65 20.65
jtag_INSTRUCTION_prog_spi_r_reg/CKB (DFCRM8NA) 0.00 20.65 f
jtag_INSTRUCTION_prog_spi_r_reg/Q (DFCRM8NA) 0.12 & 20.77 f
FE_PHC4394_n75658/Z (CKBUFM1N) 0.07 & 20.85 f
FE_PHC4393_n75658/Z (CKBUFM1N) 0.07 & 20.91 f
FE_PHC4392_n75658/Z (CKBUFM1N) 0.07 & 20.98 f
FE_PHC4391_n75658/Z (CKBUFM1N) 0.08 & 21.06 f
FE_PHC4390_n75658/Z (CKBUFM1N) 0.08 & 21.14 f
FE_PHC4389_n75658/Z (CKBUFM1N) 0.07 & 21.21 f
FE_PHC4388_n75658/Z (CKBUFM1N) 0.08 & 21.29 f
FE_PHC4395_n75658/Z (CKBUFM1N) 0.06 & 21.35 f
FE_PHC4296_n75658/Z (DEL4M4N) 0.17 & 21.53 f
FE_PHC4396_n75658/Z (BUFM3N) 0.06 & 21.58 f
FE_OFCC4612_FE_PHN3500_n75658/Z (BUFM6N) 0.07 & 21.65 f
.
.
.
中间省略200多个buffer或del
data arrival time 59.47
clock tck (rise edge) 40.00 40.00
clock network delay (propagated) 0.73 40.73
jtag_REGISTER_bypass_r_reg/CK (DFQRM1NA) 40.73 r
library setup time 0.03 40.76
data required time 40.76
------------------------------------------------------------------------------
data required time 40.76
data arrival time -59.47
------------------------------------------------------------------------------
slack (VIOLATED) -18.72