DC综合后仿真问题求教

菜鸟ASIC

小弟想用一个简单的实例来实战一下综合后仿真的步骤，但在后仿的时候遇到一下问题，请各位大侠指点一下。二分频实例：
module half_clk(reset,clk_in,clk_out);
input clk_in,reset;
output clk_out;
reg clk_out;
always@(posedge clk_in)
begin
if(!reset)  clk_out=0;
else  clk_out=~clk_out;
end
endmodule

综合后的网表为：
module half_clk ( reset, clk_in, clk_out );
  input reset, clk_in;
  output clk_out;
  wire   N4, n14, n16;
FFDHD1X clk_out_reg ( .D(N4), .CK(clk_in), .Q(n16), .QN(n14) );
  INVCLKHD8X U7 ( .A(n14), .Z(clk_out) );
  NOR2B1HDLX U8 ( .AN(reset), .B(n16), .Z(N4) );
endmodule

综合过程没有出现voilations，
通过DC导出来的SDF延时文件：
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "half_clk")
(DATE "Wed Jul  4 00:14:57 2012")
(VENDOR "smic18_ff")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "B-2008.09")
(DIVIDER /)
(VOLTAGE 1.62:1.98:1.98)
(PROCESS "worst:best:best")
(TEMPERATURE 125.00:0.00:0.00)
(TIMESCALE 1ns)
(CELL
  (CELLTYPE "half_clk")
  (INSTANCE)
  (DELAY
    (ABSOLUTE
    (INTERCONNECT reset U8/AN (0.000:0.000:0.000))
    (INTERCONNECT clk_out_reg/Q U8/B (0.000:0.000:0.000))
    (INTERCONNECT clk_out_reg/QN U7/A (0.000:0.000:0.000))
    (INTERCONNECT U8/Z clk_out_reg/D (0.000:0.000:0.000))
    (INTERCONNECT clk_in clk_out_reg/CK (0.000:0.000:0.000))
    )
  )
)
(CELL
  (CELLTYPE "NOR2B1HDLX")
  (INSTANCE U8)
  (DELAY
    (ABSOLUTE
    (IOPATH AN Z (0.133:0.100:0.100) (0.101:0.073:0.073))
    (IOPATH B Z (0.107:0.077:0.077) (0.057:0.041:0.041))
    )
  )
)
(CELL
  (CELLTYPE "INVCLKHD8X")
  (INSTANCE U7)
  (DELAY
    (ABSOLUTE
    (IOPATH A Z (1.031:0.763:0.763) (1.135:0.806:0.806))
    )
  )
)
(CELL
  (CELLTYPE "FFDHD1X")
  (INSTANCE clk_out_reg)
  (DELAY
    (ABSOLUTE
    (IOPATH (posedge CK) Q (0.287:0.219:0.219) (0.300:0.219:0.219))
    (IOPATH (posedge CK) QN (0.315:0.240:0.240) (0.294:0.215:0.215))
    )
  )
  (TIMINGCHECK
    (WIDTH (posedge CK) (0.153:0.153:0.153))
    (WIDTH (negedge CK) (0.184:0.184:0.184))
    (HOLD (posedge D) (posedge CK) (-0.052:-0.039:-0.039))
    (HOLD (negedge D) (posedge CK) (0.044:0.038:0.038))
    (SETUP (posedge D) (posedge CK) (0.097:0.071:0.071))
    (SETUP (negedge D) (posedge CK) (0.074:0.052:0.052))
  )
)
)


把DC综合后的网表和smic18.v库文件、test测试文件、加载.sdf文件之后出现一下错误：
# Loading instances from E:/EDA/KETI_WORK/work/half_clk/half_clk1.sdf
# ** Error: (vsim-SDF-3250) E:/EDA/KETI_WORK/work/half_clk/half_clk1.sdf(20): Failed to find INSTANCE 'U7'.
# ** Error: (vsim-SDF-3250) E:/EDA/KETI_WORK/work/half_clk/half_clk1.sdf(18): Failed to find INSTANCE 'U8'.
# ** Error: (vsim-SDF-3250) E:/EDA/KETI_WORK/work/half_clk/half_clk1.sdf(19): Failed to find INSTANCE 'clk_out_reg'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
# Loading work.udp_dff
# ** Fatal: SDF files require Altera primitive library
#    Time: 0 ps  Iteration: 0  Instance: /top_test File: E:/EDA/KETI_WORK/work/half_clk/top_test.v
# FATAL ERROR while loading design
# Error loading design



请问以上错误是什么原因，我只加载网表之后，有波形出来，波形跟前仿结果一样，但同时加载SDF文件后，就出现ERROR loading design，请各位大侠指点一下，多谢了、

bukubuku

是不是$sdf_annotate参数里那个instance name写错了

菜鸟ASIC

回复 2# bukubuku


   啥意思呢？能解释清楚一点吗？在哪里改这个参数呢？求再赐教，多谢了

daisyniu

综合后仿真要读入标准单元的.v文件

atm123

学习一下

my2817

附上仿真脚本吧

dennisi123

我也遇到了相同的问题，求高手解答！

flyloop

综合后的网表仿真 太难搞了

myCollins

学习一下

marco0109

不錯的訊息 謝謝分享