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发表于 2012-7-3 14:30:15
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Verdi is a superset of Debussy.
The various modules/features of Verdi are
nCompare - Waveform compare (compare rtl and gate level waveforms).
nSchema - Schematic browser(delay annotation).
nState - State Diagram Debugger (Displays the Bubble Diagram of state machines)
n Analyzer - Debug clock tree, clock and reset analysis,view multiple clock domains.
nEco - Evaluate the changes made on the fly and validate them.
SVTB - Gives the System Verilog Test Bench Inheritance view, class variables can be viewed synchronously with other signals on nWave.
Assertion Evaluator - Evaluates System Verilog assertions off line without the simulator.
Power Manager - Debug the UPF and CPF files and visualize the different power domains in the design
Temporal Flow Wiew - Brings time,value and hierarchy on the same window |
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