Encounter CTS 遇到的问题

pastchen

在encounter里作CTS的时候，长完clock tree, clockDesign自己作post CTS opt时遇到这个问题，哪位高手能指点一下
*** End ckSynthesis (cpu=0:22:34, real=0:22:33, mem=2795.9M) ***
<clockDesign CMD> specifyClockTree -update {AutoCTSRootPin * PostOpt YES}
<clockDesign CMD> ckECO -postCTS -useSpecFileCellsOnly -report clock_report_32/clock.postCTS.report
Redoing specifyClockTree ...
Checking spec file integrity...
**ERROR: (ENCCK-176):   The design has not been routed.
**ERROR: (ENCCK-2201):  ckECO is stopped by clock nets are not fully routed. Please resolve it before running ckECO
*** End ckECO (cpu=0:00:00.1, real=0:00:00.0, mem=2800.9M) ***
**clockDesign ... cpu = 0:22:40, real = 0:22:40, mem = 2800.9M **

整个design有多个clk，以下是其中一个clk的ctstch
#------------------------------------------------------------
# Clock Root   : clk_ctrl/i_div2_dont/Q
# Clock Name   : eclk
# Clock Period : 5.4ns
# Clock Name   : eclk
# Clock Period : 5.4ns
#------------------------------------------------------------
AutoCTSRootPin clk_ctrl/eclk_BUF_1/C
Period         5.4ns
MaxDelay       1ns # sdc driven default
MinDelay       0ns # sdc driven default
MaxSkew        200ps # set_clock_uncertainty
SinkMaxTran    300ps # set_clock_transition
BufMaxTran     300ps # set_clock_transition
Buffer         CKBD12 CKBD16 CKBD6 CKBD8
NoGating       NO
DetailReport   YES
MaxFanout      32
#SetDPinAsSync  NO
#SetIoPinAsSync NO
#SetASyncSRPinAsSync  NO
#SetTriStEnPinAsSync NO
#SetBBoxPinAsSync NO
RouteClkNet    YES
PostOpt        YES
OptAddBuffer   YES
RouteType      specialRoute
LeafRouteType  regularRoute
END

pastchen

回复 1# pastchen


    有哪位能推测下问题出在哪么？公司转encounter，作CTS的时候遇到这个问题，困扰好几天了

gaohb9988

确认 clock nets routing 了没有，如果routing了用 -clockRouteOnly

pastchen

回复 3# gaohb9988


    看了下，clock tree就没有route, 本来place opt后有global route， cts的时候它自己删掉了，它自己再做global route的时候就出错了

陈涛

做CTS前，setCtsMode -routeClkNet true
做CTS时，确认encounter有nanoroute license
做CTS后，zoom in 确认clock net 是routed的，选一条clock wire，"q"看属性，是否为routed

iuqq205

一般的检查你可以看看你的选项。
我提供一种比较特殊的情况供你分析：是不是把route type对应的top/bottom layer限制的太严，比如只用了M4/M5route，但是工具却无法穿过BLOCK（memory等），导致到memory的clock net无法route。

pastchen

回复 6# iuqq205


   应该不是这个问题，我设了
# trial route
setTrialRouteMode -maxRouteLayer 6
setTrialRouteMode -minRouteLayer 2

setCTSMode -routeBottomPreferredLayer 2 -routeTopPreferredLayer 6
setCTSMode -routeLeafBottomPreferredLayer 2 -routeLeafTopPreferredLayer 6

另外能解释下 extraspace值的设定么
setCTSMode -routePreferredExtraSpace 0 ;#default=1
setCTSMode -routeLeafPreferredExtraSpace 0 ;#default=1
这个设为1是不是在原有space的基础上额外增加1倍的sapce，那这样的话我是不是可以直接就用setCTSMode -routePreferredExtraSpace 1，不用再设定double_space了？

pastchen

另外我的clockDesign自己调用的CMD过程很困惑。
这是整个CTS的CMD
<CMD> win
<CMD> restoreDesign db/split_full.enc.dat S60D2
<CMD> initNdr
<CMD> setNdrSpacing -layer M1 0.24
<CMD> setNdrSpacing -layer M2 0.28
<CMD> setNdrSpacing -layer M3 0.28
<CMD> setNdrSpacing -layer M4 0.28
<CMD> setNdrSpacing -layer M5 0.28
<CMD> setNdrSpacing -layer M6 0.84
<CMD> setNdrSpacing -hardSpacing 0
<CMD> createNdr double_spacing
<CMD> all_constraint_modes -active
<CMD> set_interactive_constraint_modes [all_constraint_modes -active]
<CMD> set_dont_touch_network [get_clocks *]
<CMD> set_dont_touch false [get_lib_cells CKBD*]
<CMD> set_dont_use false [get_lib_cells CKBD*]
<CMD> set_clock_transition 0.3 [all_clocks]
<CMD> set_clock_uncertainty 0.2 [all_clocks]
<CMD> set_max_fanout 32 [current_design]
<CMD> setDesignMode -process 90nm
<CMD> setCTSMode -routeNonDefaultRule double_spacing
<CMD> setCTSMode -routeBottomPreferredLayer 1 -routeTopPreferredLayer 6
<CMD> setCTSMode -routeLeafBottomPreferredLayer 2 -routeLeafTopPreferredLayer 6
<CMD> clockDesign -skipTimeDesign -specFile /proj/Clock.ctstch -outDir clock_report -fixedInstBeforeCTS
<clockDesign CMD> cleanupSpecifyClockTree
<clockDesign CMD> specifyClockTree -file /proj/Clock.ctstch
<clockDesign CMD> changeClockStatus -all -fixedBuffers
<clockDesign CMD> deleteClockTree -all
<clockDesign CMD> ckSynthesis -report clock_report/clock.report -forceReconvergent -breakLoop
<clockDesign CMD> specifyClockTree -update {AutoCTSRootPin * PostOpt YES}
<clockDesign CMD> ckECO -postCTS -useSpecFileCellsOnly -report clock_report/clock.postCTS.report

既然changeClockStatus -all -fixedBuffers  那还怎么deleteClockTree -all
log也显示出了问题deleteClockTree Option :  -all
*** 1 Buffers found to be either having FIXED attribute or constraints on it. deleteClockTree may not delete them.***
*** Use changeClockStatus to change the FIXED status. ***
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/clk_BUF_3/C.
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/bist_clk_dont/Z.
*** 1 Buffers found to be either having FIXED attribute or constraints on it. deleteClockTree may not delete them.***
*** Use changeClockStatus to change the FIXED status. ***
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/apclk_BUF_1/C.
*** 1 Buffers found to be either having FIXED attribute or constraints on it. deleteClockTree may not delete them.***
*** Use changeClockStatus to change the FIXED status. ***
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/oclk_BUF_1/C.
*** 1 Buffers found to be either having FIXED attribute or constraints on it. deleteClockTree may not delete them.***
*** Use changeClockStatus to change the FIXED status. ***
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/lclk_0__BUF_1/C.
*** 1 Buffers found to be either having FIXED attribute or constraints on it. deleteClockTree may not delete them.***
*** Use changeClockStatus to change the FIXED status. ***
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/lclk_1__BUF_1/C.
*** Removed (0) buffers and (0) inverters in Clock clk_ctrl/eclk_BUF_1/C.

小豆丁

学习了~~~~

iuqq205

回复 7# pastchen


   CTS如果要route net默认情况下是调用nanoroute。和你trialRoute设置无关。   你ckEco如果跑不起来，建议你看看是什么线没有route。再进一步分析