Design and Modeling of PLL Based CDR for Inter Chip Communications

xhseu

Design and Modeling of PLL Based CDR for Inter Chip Communications  http://www.amazon.com/Design-Modeling-Based-Communications-Verilog/dp/3639185544  谁有这本书？ 谢谢

过路心客

这是篇论文。国外写得好的论文，也可以找出版社直接出版。 abbr_df29135f9d47a5983f9de9169d6f41c1.pdf (8.57 MB, 下载次数: 2448 )

2011-12-12 19:41 上传

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Design and Modelling of Clock and Data Recovery Integrated Circuit in 130nm CMOS Technology for 10Gb ...

过路心客

文件名为什么会变成乱的？
Design and Modelling of Clock and Data Recovery Integrated Circuit in 130nm CMOS Technology for 10Gbs Serial Data Communications [Assaad 2009].pdf

fixit

thanks

Jason.tschen

very well
I am very appreciated with your post , thanks buddy

sunjimmy

Thanks for sharing the PhD thesis.
Good job !

harry1862pd

Thanks for sharing the PhD thesis.
Good job !

qchunh

xiexie

leonken460

thanks a loot

aak

感謝提供分享, 下來參考看看